Typically, simulation models are generated from abstract data sheet diagrams and specifications. While the resulting model captures the intended logical function of the design, it often fails to capture problems associated with the actual design (e.g., wiring errors, logic cell design errors, timing problems, etc., in the physical implementation). Also, the model may not provide an accurate basis for fault selection and test generation, since it is not based on the physical circuit. Thus, the actual physical design should be the starting point for generating accurate functional and fault models.
Sp2log translates a Spice level circuit description (usually obtained by extraction from the layout) into a gate and switch representation. Switches are only used in this representation when a gate (including tristate functions) cannot be generated.
Pattern recognition (transistor topology) is not used for gate reduction. Instead, boolean equations are generated representing the pullup and pulldown paths. Boolean algebra and conflict resolution routines determine where gates reside. This approach eliminates teh complicated rules associated with topological matching and ultimately produces a better mapping of functionality
Even in a "purely digital" design, there are suubcircuits whose behavior is sufficiently non-digital to confuse a switch-level logic simulator. Typically, these subcircuits reside in the pad circuitry; TTL level shifters and Schmitt trigger inputs are examples. Analog functions such as memory sense amplifiers and voltage comparators are examples of other "troublesome" subcircuits. Sp2log recognizes analog transistor biasing, and transforms these subcircuits into a digital equivalent for the model.
Sp2log utilizes a flexible method for approximating gate delays. A postprocessore can "tweak" the delays to make them more accurate, if necessary. Sp2log provides a good estimation of the distribution of delays throughout the circuit. This is very important for modeling single-input pulse handling characteristics and multi-input setup and hold characteristics. Distributed delays are necessary for properly modeling subcircuits such as inverter chains, one-shots, and blocks with many levels of logic between their input and output signals.
Sp2log has been tested on more than 150 digital cells in an ASIC library, from simple cates to the Advancell 2900 bit slice family. It successfully reduced all Spice descriptions in this library to 100% gate level equivalents. Sp2log has also been used on a number of large custom designs with excellent results. The small amount of switches that were used was needed to represent the true bi-lateral operation in some RAM cells.
When Spwlog is used in conjunction with the delay characterization program, Gendel, the resulting models are extremely accurate in functionality and timing.
See our paper from Async94 Tools for Validating Asynchronous Digital Circuits for more information on how Sp2log can be used.