Delay Table Generator for Accurate Timing Characterization
One of the most time-consuming tasks in generating simulation models for a library of cells is timing characterization. A cell may be asked to operate with a wide range of output loading and input slew-rate conditions in a design. It requires a large number of simulations for each cell in the library to capture this information.
Typically, each cell is simulated using a circuit-level simulator multiple times, each with changes in the operating point for the cell. The resultant timing is measured from these simulations and then fit to an equation or curve(s) that represents the timing of the cell for a variety of differing operating conditions.
The final accuracy of timing or delays used in logic simulation depends on:
Realize that for a typical library consisting of over 150 cells, this process can be a formidable task.
Gendel provides a means of reducing the complexity and number of simulations required to model delays of the library without sacrificing accuracy.
By intelligently analyzing cell behavior and optimizing the characterization process, Gendel dramatically reduces the time and effort required for timing characterization while maintaining the accuracy needed for reliable simulation results.
Minimize the number of circuit-level simulations required without compromising timing accuracy.
Dramatically reduce the time required to characterize large cell libraries.
Achieve accurate delay modeling across wide ranges of operating conditions.
Handle libraries with 150+ cells efficiently, making large-scale characterization practical.
Model cell timing across varied output loading and input slew-rate conditions.
Works with Sp2log to provide extremely accurate functionality and timing models.
Gendel played an important role in the University of Manchester collaboration on asynchronous ARM processor design. Accurate timing characterization is critical for asynchronous circuits where timing relationships determine correct operation.
The tool's ability to efficiently generate accurate delay models enabled the rapid iteration and optimization required for the successful development of the clockless ARM design.
When Gendel is used in conjunction with Sp2log, the combination provides extremely accurate models in both functionality and timing. Sp2log handles the functional model generation from layout-extracted SPICE netlists, while Gendel provides the precise timing characterization.
The delay tables generated by Gendel are used by the Simic Logic Simulator to provide accurate timing simulation. This ensures that simulation results reflect the actual timing behavior of the physical implementation.
Minimize required simulations through smart analysis of cell behavior.
Generate timing models that accurately represent cell behavior across operating conditions.
Handle varying output loads and input slew rates comprehensively.
Efficiently characterize libraries with hundreds of cells.
For more information about Gendel and its application in timing characterization:
For more information about Gendel, please contact: support@genashor.com