SPICE to Logic Compiler - Bridge Between Analog and Digital Design
Typically, simulation models are generated from abstract data sheet diagrams and specifications. While the resulting model captures the intended logical function of the design, it often fails to capture problems associated with the actual design - wiring errors, logic cell design errors, timing problems, and other issues in the physical implementation.
Additionally, the model may not provide an accurate basis for fault selection and test generation, since it is not based on the physical circuit. Thus, the actual physical design should be the starting point for generating accurate functional and fault models.
Sp2log translates a SPICE-level circuit description (usually obtained by extraction from the layout) into a gate and switch representation. Switches are only used in this representation when a gate (including tristate functions) cannot be generated.
This approach ensures that the simulation model accurately reflects the physical implementation, capturing real-world behaviors that abstract models might miss.
Pattern recognition (transistor topology) is not used for gate reduction. Instead, boolean equations are generated representing the pullup and pulldown paths. Boolean algebra and conflict resolution routines determine where gates reside.
This approach eliminates the complicated rules associated with topological matching and ultimately produces a better mapping of functionality. The result is more accurate models that truly represent the physical circuit's behavior.
Even in a "purely digital" design, there are subcircuits whose behavior is sufficiently non-digital to confuse a switch-level logic simulator. Typically, these subcircuits reside in the pad circuitry - TTL level shifters and Schmitt trigger inputs are common examples. Analog functions such as memory sense amplifiers and voltage comparators are other "troublesome" subcircuits.
Sp2log recognizes analog transistor biasing and transforms these subcircuits into digital equivalents for the model. This intelligent handling of mixed-signal circuits enables accurate simulation of complete designs without requiring manual intervention.
Sp2log utilizes a flexible method for approximating gate delays. A postprocessor can refine the delays to make them more accurate if necessary. Sp2log provides a good estimation of the distribution of delays throughout the circuit.
This distributed delay modeling is critical for:
Sp2log has been tested on more than 150 digital cells in an ASIC library, from simple gates to the Advancell 2900 bit slice family. It successfully reduced all SPICE descriptions in this library to 100% gate level equivalents.
Sp2log has also been used on a number of large custom designs with excellent results. The small amount of switches that were needed represented the true bilateral operation in some RAM cells - a testament to the tool's ability to maximize gate-level representation.
When Sp2log is used in conjunction with the delay characterization program Gendel, the resulting models are extremely accurate in both functionality and timing.
This powerful combination provides designers with models that truly represent their physical implementations, enabling accurate verification before fabrication and reducing the risk of silicon failures.
Generates models from extracted SPICE netlists, ensuring accuracy based on physical implementation.
Uses boolean algebra instead of pattern matching for superior gate reduction and functionality mapping.
Automatically recognizes and converts analog subcircuits to digital equivalents.
Accurate timing representation throughout the circuit for proper verification.
Maximizes gate-level representation, minimizing switch-level primitives.
Successfully tested on 150+ library cells and numerous custom designs.
For more information about Sp2log and its application in IC design:
For more information about Sp2log, please contact: support@genashor.com