BTGRN
Resistive bidirectional switch, positive enabled (closed when C=1).
Model
Note: The zigzag line represents the resistive element between the bidirectional ports.
Description
The BTGRN primitive is a non-ideal switch element with configurable ON-resistance. The resistance is specified by assigning a SERIES-DEPTH (SDEPTH) value upon instantiating the switch in a SNL PART statement.
BTGRN: Enabled when its control input, C, is a logical-1 (positive enabled)
The SDEPTH value can range from 1 to 32766, where:
- 1 = minimum resistance of the switch
- 32766 = maximum resistance of the switch
- If unspecified, the SDEPTH value defaults to 1
| C (Control) | BTGRN State |
|---|---|
| 0 | Open |
| 1 | Closed (resistive) |
| X | Unknown |
Charge Storage Considerations
It is important that charge-storage be modeled reasonably in switch networks (i.e. decays are larger than delays), otherwise the simulation could produce transient X pulses, slowing down the simulation throughput and possibly generating oscillations during network value convergence.
Compiler Optimization
SIMIC optimizes switch level networks during compilation:
- Merging paralleled gates
- Converting bidirectional BTGRNs to unidirectional UTGRNs where possible
This optimization improves simulation throughput by reducing bidirectional signal propagation to unidirectional flow where the circuit topology allows it.
Equivalent Type Statement
Type=BTGRN i=C b=B[1],B[2] sdepth=1
Example Usage
PART=sw1 TYPE=btgrn I=ctrl B=in,out SDEPTH=1
PART=sw2 TYPE=btgrn I=enable B=node_a,node_b SDEPTH=5
Notes
- BTGRN is a resistive switch with configurable ON-resistance
- This switch is bidirectional—signal flow can occur in either direction
- The SDEPTH parameter controls the switch's ON-resistance (1=minimum, 32766=maximum)
- SIMIC automatically converts BTGRNs to unidirectional UTGRNs where possible for better performance
- For negative enabled resistive switch, see BTGRP primitive
- For ideal switches with zero resistance, see BTGN and BTGP primitives
- Proper charge storage modeling (decays > delays) is essential to avoid transient X pulses