Built-in Primitives Catalog

A reference table of all built-in logic and memory elements.

Simple Combinatorial Gates

Type Description Pin Order
INV Inverter gate i=I o=Q
AND AND gate i=I[1:1-32767] o=Q
NAND NAND gate i=I[1:1-32767] o=Q
OR OR gate i=I[1:1-32767] o=Q
NOR NOR gate i=I[1:1-32767] o=Q
EXOR Exclusive-OR gate i=I[1:1-32767] o=Q
EXNOR Exclusive-NOR gate i=I[1:1-32767] o=Q

Combinatorial Functions

Type Description Pin Order
AANOR AND-AND-NOR function i=A[1:2],B[1:2] o=Q
OONAND OR-OR-NAND function i=A[1:2],B[1:2] o=Q
MUX 2-input Multiplexer function i=A,B,C o=Q

Latches

Type Description Pin Order
NANDL NAND latch i=R,S o=Q
NORL NOR latch i=R,S o=Q
DPL, DL D latch with positive clock i=NR,NS,C,D o=Q
DNL D latch with negative clock i=NR,NS,C,D o=Q

Flip-Flops

Type Description Pin Order
DPCF, DCF D flip-flop with positive clock i=NR,NS,C,D o=Q
DNCF D flip-flop with negative clock i=NR,NS,C,D o=Q
JKNCF, JKCF JK flip-flop with negative clock i=NR,NS,C,J,K o=Q
JKPCF JK flip-flop with positive clock i=NR,NS,C,J,K o=Q
TNCF, TCF T flip-flop with negative clock i=NR,NS,T o=Q
TPCF T flip-flop with positive toggle i=NR,NS,T o=Q

Tristate Functions

Type Description Pin Order
TGATE P-N totem tristate driver i=P,N o=Q
TINVN Tristate inverter, high enable i=EN[1:1-14],D o=Q
TINVP Tristate inverter, low enable i=EN[1:1-14],D o=Q
TPADN Tristate buffer, high enable i=EN[1:1-14],D o=Q
TPADP Tristate buffer, low enable i=EN[1:1-14],D o=Q

Programmable Functions and Memories

Type Description Pin Order
BOOLEAN User-definable function i=I[1:N] o=Q[M]
ROM ROM element i=CS,RE,WE,AE,ADDR[0-15:0] o=DATA[0-99:0]
RAMA RAM element with clocked write i=CS,RE,WE,C,ADDR[0-15:0],DATAIN[0-99:0] o=DATA[0-99:0]
RAMB RAM (RAMC with separate read and write address lines) i=CS,RE,WE,RADDR[0-15:0],WADDR[0-15:0],DATAIN[0-99:0] o=DATA[0-99:0]
RAMC RAM with Address Enable i=CS,RE,WE,AE,ADDR[0-15:0],DATAIN[0-99:0] o=DATA[0-99:0]
PLA User-definable PLA element i=CS,EN,I[1:1-32767] o=Q[1:1-32767]

Switches

Type Description Pin Order
BTGN, BTG Ideal Bidirectional switch enabled when I is logical-1 i=I b=B[1:2]
BTGP Ideal Bidirectional switch enabled when I is logical-0 i=I b=B[1:2]
BTGRN Resistive Bidirectional switch enabled when I is logical-1 i=I b=B[1:2]
BTGRP Resistive Bidirectional switch enabled when I is logical-0 i=I b=B[1:2]
UTGRN Resistive Unidirectional switch enabled when I is logical-1 i=EN,D o=Q
UTGRP Resistive Unidirectional switch enabled when I is logical-0 i=EN,D o=Q

Backannotation Elements

Type Description Pin Order
DELAY Path delay element i=I o=Q
LOAD, NET Net loading element for backannotation o=Q

Signal Merge Elements

Type Description Pin Order
JOIN Wire jumper that creates signal aliases i=I[1:1-32767]