DNL / DNPL (D Latch)

D latch with negative clock. Level-sensitive D-type latch with active-low set/reset.

LATCH

Model

Operation

The latch is **transparent** when the clock (C) is Low (0). It latches the value on the rising edge of C. Any prefix of DNL or DNPL can be used to reference this primitive.

Note: DL is the positive clock version, which is transparent when C is High (1).

NR	NS	C	D	Q (Next)	Comment
0	1	—	—	0	Reset (Async)
1	0	—	—	1	Set (Async)
0	0	—	—	1*	Dominant Set
1	1	0	0	0	Transparent 0
1	1	0	1	1	Transparent 1
1	1	1	—	Latched	Storage Mode
X/Z	1	—	—	X (unless Q=0)	Unknown Reset

*Note: Set dominates when both NR and NS are low.

Timing Checks

Timing checks can be assigned by a TIMING-CHECKS block. Simic verifies the following constraints for DNL:

SETUP: Specifies the duration that an input must be stable prior to the active clock change (rise).
- SETUP.D: Setup from data.
- SETUP.NR: Setup from trailing edge of reset when data=1.
- SETUP.NS: Setup from trailing edge of set when data=0.
HOLD: Specifies the duration that an input must be stable after the active clock change (rise).
- HOLD.D: Hold from data.
- HOLD.NR: Hold from reset.
- HOLD.NS: Hold from set.
PULSE-WIDTHS: Specifies the minimum width of a pulse on control lines.
- PW.NR, PW.NS: Pulse-width reset/set.
- PW.C.H, PW.C.L: High and low pulse-width clock.

Unspecified timing checks default to 0 (disabled).

Example Usage

part=FF1 type=DNL i=reset,set,clk,data o=q1 $
timing-checks= $
BEGIN; $
    SETUP = 5;      $ # All setups are 5 units
    HOLD.D = 10;    $ # Hold from D is 10
    HOLD = 5;       $ # All other holds are 5
    PW = 4;         $ # All pulse-widths are 4
    PW.C.L = 3;     $ # Clock-low pulse-width is 3
END;

Equivalent Type Statement

Type=DNL i=NR,NS,C,D o=Q
Type=DNPL i=NR,NS,C,D o=Q