RAMC

RAM primitive with separate Address Enable (AE).

MEMORY

Model

Pin	Function
`CS`	Chip Select (Active High). If Low, outputs are High-Z and writes are disabled.
`RE`	Read Enable (Active High). Enables level-sensitive read from memory.
`WE`	Write Enable (Active High). Enables level-sensitive write to memory.
`AE`	Address Enable. When High, internal address register tracks `ADDR`; when Low, address is latched.
`ADDR`	Address input bus.
`DATAIN`	Data input bus for writes.
`DATA`	Data output bus for reads.

Operation

RAMC provides an independent **Address Enable (AE)** signal. When AE is low, the address inputs are ignored, and the internal address register is held.

AE	ADDR	Internal Address
0	—	Unchanged
1	New Value	New Value

Initialization & Data Population

RAMC is initialized using the DATA keyword in the PART statement, or dynamically prior to simulation using the CLAMP command.

# Static initialization in netlist
PART=U1 TYPE=RAMC DATA=X0, FF, 00, AA, 55

# Dynamic population in run script
CLAMP PART=U1 DATA=X0 FF

For detailed information on DATA syntax, X-handling, and the CLAMP command, see the Memory Handling & Initialization guide.

X-Handling

Address Enable (AE): If AE is X, the internal address state becomes unknown, forcing the output data bus to X if the read is enabled. Any write during AE=X sets all potentially targeted memory locations to X.
Read/Write: Follows the same logic as RAMA, with the additional dependency on the AE state.

Physical Constraints

Address Latching: The internal address register is updated from the ADDR bus only when AE=1.
Bus Consistency: ADDR[m:0] defines the address space, and DATAIN[n:0]/DATA[n:0] define the word size.

Equivalent Type Statement

Type=RAMC i=CS,RE,WE,AE,ADDR[m:0],DATAIN[n:0] o=DATA[n:0]