RAMA

Single Port RAM primitive with clocked write.

MEMORY

Model

Pin	Function
`CS`	Chip Select (Active High). If Low, outputs are High-Z and writes are disabled.
`RE`	Read Enable (Active High). If Low, outputs are High-Z.
`WE`	Write Enable (Active High). Enables memory write on rising clock edge.
`C`	Clock. Rising edge triggers memory write.
`ADDR`	Address input bus.
`DATAIN`	Data input bus for writes.
`DATA`	Data output bus for reads.

Data is written to the RAM on the **rising clock edge** when Chip Select (CS) and Write Enable (WE) are high.

RAM contents can be initialized prior to simulation via the DATA keyword in the PART statement or dynamically using the CLAMP command:

# Static initialization in netlist
PART=U1 TYPE=RAMA DATA=X0, 00, 01, 02, 03

# Dynamic population in run script
CLAMP PART=U1 DATA=X1FC AA BB CC

For detailed information on the DATA syntax, X-handling behavior, and the CLAMP command, see the Memory Handling & Initialization guide.

Read: If CS or RE is X, the output bus is X. If any address bit is X, Simic reads all matching locations; if values differ, the result is X.
Write: If CS and WE are 1, and the clock C has an X-transition, or if address bits are X during a valid write, all matching memory locations are set to X.
If the number of X-bits in the address exceeds MAXX, the operation (read or write) forces the memory state or output to X immediately.

Address Depth: Supports 2^m+1 locations.
Data Width: DATAIN and DATA buses must have the same width (n+1 bits).
Timing: While RAMA uses a functional clock C, it is subject to global timing parameters if TIMING_CHECKS are enabled for the model.

Type=RAMA i=CS,RE,WE,C,ADDR[m:0],DATAIN[n:0] o=DATA[n:0]