Memory Handling & Initialization

Data Population

Simic supports two primary methods for populating memory primitives (ROM, RAMA, RAMB, RAMC): static initialization in the netlist and dynamic initialization via the CLAMP command.

1. Static Netlist Initialization

Use the DATA keyword within the PART statement in your .net file. Data is provided as a comma-separated list of hexadecimal values.

PART=U1 TYPE=ROM I=... O=... DATA=X0, FF, AA, X4, 01

2. Dynamic Command Initialization (CLAMP)

Pre-simulation RAM or ROM initialization is performed using the CLAMP command. This is the preferred method for loading program code or firmware from a .run file.

# Syntax: CLAMP PART=<name> DATA=X<addr> <data> ...
# Example: Load code starting at address 0x0000 and 0xC000
CLAMP PART=RAM1 DATA=X0000 00 01 02 03 04 05 06 07 $
                     08 09 0A 0B 0C 0D 0E 0F $
                     XC000 FF FF FF FF

The DATA Syntax

• Hexadecimal Values: (e.g., FF, 01) Hexadecimal digits representing a memory word. The internal address counter increments automatically after each word.
• Address Markers (X): (e.g., X0000, XC000) Sets the current address counter for subsequent data words.
• Continuation ($): Use the $ character to continue a long DATA string onto the next line.
• Bit Truncation: If a hex value provides more bits than the memory word width, higher-order bits are truncated with a warning.

X-Handling Logic

Simic uses sophisticated logic to handle unknown (X) states on control and address lines, balancing accuracy with simulation performance.

Address Line X-States

If any bit of the address bus is in an X state:

• Read Operation: Simic identifies all possible physical addresses that satisfy the known bits. If the data bits at all matching addresses are identical, that value is output. If any bit differs across the matching set, that bit is set to X on the output bus.
• Write Operation: Every memory location satisfying the address pattern (including those with X-bits) is set to X.
• Effiency Limit (MAXX): If the number of X bits on the address bus exceeds the global MAXX limit (default is typically 4-8 depending on configuration), Simic flushes the entire memory to X (for write) or sets the output to X (for read) to avoid exponential evaluation costs.

Control Line X-States

• If Chip Select (CS) is X, the memory output is forced to X (floating or unknown).
• If Write Enable (WE) is X during a valid chip-select and clock event, the target memory location is set to X.

Sparse Memory Allocation

Simic utilizes a sparse allocation technique for large memory primitives. Memory is allocated in 1024-word pages only when a write operation occurs to a specific address range. This allows simulation of systems with large address spaces (e.g., 32-bit address buses) as long as the utilized memory remains within the host machine's physical limits.

[!NOTE] Large static initializations using DATA in the netlist will cause these pages to be allocated during simulation startup, which may increase initial memory footprint.