DPCF (D Flip-Flop)

D flip-flop with positive clock. Positive-edge-triggered master-slave D flip-flop with active-low set/reset.

FLIP-FLOP

Model

Note: Set (NS) and Reset (NR) inputs are active-low. Set dominates when both are low.

Truth Table

The DPCF handles asynchronous Set/Reset and synchronous Data latching on the positive (rising) edge of the clock. 4-value logic (0, 1, X, Z) is supported on all pins.

Note: DNCF is the negative clock version, which triggers on the falling edge of C.

NR	NS	C	D	Q (Next)	Comment
0	1	—	—	0	Reset (Async)
1	0	—	—	1	Set (Async)
0	0	—	—	1*	Dominant Set
1	1	↑	0	0	Latch 0
1	1	↑	1	1	Latch 1
1	1	↑	X/Z	X	Latch Unknown
1	1	0/1	—	Q	No Change
X	1	—	—	X (unless Q=0)	Unknown Reset

*Note: Set dominates when both NR and NS are low.

Timing Checks

Timing checks can be assigned by a TIMING-CHECKS block. Simic verifies the following constraints for DPCF:

SETUP: Specifies the duration that an input must be stable prior to the active clock edge (rise).
- SETUP.D: Setup from data.
- SETUP.NR: Setup from trailing edge of reset when data=1.
- SETUP.NS: Setup from trailing edge of set when data=0.
HOLD: Specifies the duration that an input must be stable after the active clock edge (rise).
- HOLD.D: Hold from data.
- HOLD.NR: Hold from reset.
- HOLD.NS: Hold from set.
PULSE-WIDTHS: Specifies the minimum width of a pulse on control lines.
- PW.NR, PW.NS: Pulse-width reset/set.
- PW.C.H, PW.C.L: High and low pulse-width clock.

Unspecified timing checks default to 0 (disabled).

Example Usage

part=FF1 type=DPCF i=reset,set,clk,data o=q1 $
timing-checks= $
BEGIN; $
    SETUP = 5;      $ # All setups are 5 units
    HOLD.D = 10;    $ # Hold from D is 10
    HOLD = 5;       $ # All other holds are 5
    PW = 4;         $ # All pulse-widths are 4
    PW.C.L = 3;     $ # Clock-low pulse-width is 3
END;

Equivalent Type Statement

Type=DPCF i=NR,NS,C,D o=Q
Type=DCF i=NR,NS,C,D o=Q

Note: DCF is an alias for DPCF.