JKPCF
JK flip-flop with positive clock. Positive-edge-triggered master-slave JK flip-flop with active-low set/reset.
Model
Truth Table
The JKPCF handles asynchronous Set/Reset and synchronous JK
transitions. It is
positive-edge-triggered. Any prefix of JKPCF can be used.
Note: JKCF is the negative clock version, which triggers on the falling
edge of C.
| NR | NS | C | J | K | Q (Next) |
|---|---|---|---|---|---|
| 0 | 1 | — | — | — | 0 (Reset) |
| 1 | 0 | — | — | — | 1 (Set) |
| 0 | 0 | — | — | — | 1* (Dominant Set) |
| 1 | 1 | ↑ | 0 | 0 | Q (No Change) |
| 1 | 1 | ↑ | 0 | 1 | 0 (Reset) |
| 1 | 1 | ↑ | 1 | 0 | 1 (Set) |
| 1 | 1 | ↑ | 1 | 1 | Q (Toggle) |
| 1 | 1 | 0/1 | — | — | Q |
*Note: Set dominates when both NR and NS are low.
Timing Checks
Timing checks can be assigned by a TIMING-CHECKS block. Simic verifies the following
constraints for JKPCF:
- SETUP: Specifies the duration that an input must be stable prior to the active
clock edge (rise).
SETUP.J,SETUP.K: Setup from J and K.SETUP.NR: Setup from trailing edge of reset when logic-1 is clocked-in.SETUP.NS: Setup from trailing edge of set when logic-0 is clocked-in.
- HOLD: Specifies the duration that an input must be stable after the active clock
edge (rise).
HOLD.J,HOLD.K: Hold from J and K.HOLD.NR: Hold from reset.HOLD.NS: Hold from set.
- PULSE-WIDTHS: Specifies the minimum width of a pulse on control lines.
PW.NR,PW.NS: Pulse-width reset/set.PW.C.H,PW.C.L: High and low pulse-width clock.
Unspecified timing checks default to 0 (disabled).
Example Usage
part=FF1 type=JKPCF i=reset,set,clk,j,k o=q1 $
timing-checks= $
BEGIN; $
SETUP = 5; $ # All setups are 5 units
HOLD.J = 10; $ # Hold from J is 10
HOLD = 5; $ # All other holds are 5
PW = 4; $ # All pulse-widths are 4
PW.C.L = 3; $ # Clock-low pulse-width is 3
END;Equivalent Type Statement
Type=JKPCF i=NR,NS,C,J,K o=Q