PLA (Programmable Logic Array)
Configurable AND-OR matrix for complex logic implementation.
Model
| Pin | Function |
|---|---|
CS |
Chip Select (Active High). If Low, outputs are High-Z. |
EN |
Output Enable. If Low, outputs show default value (usually 0). |
I[1:n] |
Data Inputs. |
Q[1:m] |
Data Outputs. |
Configuration
The PLA is configured using three specialized keywords: AND, OR, and
BITMAP.
1. Plane Sizes
Define the number of product terms and matrix size.
AND [inputs-2] * [products]
OR [products] * [outputs]2. Bitmaps
The BITMAP keyword specifies the connections for the plane currently being configured. Each
entry is a string of 0, 1, or X (no connection).
BITMAP "01X01..." ; Product 1
BITMAP "1100X..." ; Product 2Comprehensive Example: BCD to 7-Segment Decoder
This implementation converts a 4-bit BCD digit (Q[3:0]) into control signals for a seven-segment display. It demonstrates logical encoding, product term minimization, and the use of complemented connections in the OR plane.
Display Mapping
The segments are indexed 7 through 1 as follows:
Truth Table (Digits 0-9)
| Digit | Q[3:0] | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
|---|---|---|---|---|---|---|---|---|
| 0 | 0000 | 1 | 1 | 0 | 1 | 1 | 1 | 1 |
| 1 | 0001 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
| 2 | 0010 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
| 3 | 0011 | 1 | 0 | 1 | 1 | 0 | 1 | 1 |
| 4 | 0100 | 0 | 1 | 1 | 1 | 0 | 1 | 0 |
| 5 | 0101 | 1 | 1 | 1 | 0 | 0 | 1 | 1 |
| 6 | 0110 | 1 | 1 | 1 | 0 | 1 | 1 | 1 |
| 7 | 0111 | 1 | 0 | 0 | 1 | 0 | 1 | 0 |
| 8 | 1000 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| 9 | 1001 | 1 | 1 | 1 | 1 | 0 | 1 | 1 |
Boolean Equations
Based on the segment logic, the equations are as follows:
SEG[7] = Q[3] + Q[2]*^Q[1] + Q[2]*^Q[0] + ^Q[2]*Q[1]
SEG[6] = Q[3] + Q[2]*^Q[1]*Q[0] + ^Q[2]*^Q[0] + Q[1]
SEG[5] = Q[3] + Q[2]*^Q[1] + ^Q[1]*^Q[0]
SEG[4] = ^Q[2]*^Q[0] + Q[1]*^Q[0]
SEG[3] = Q[2]*^Q[1]*Q[0] + ^Q[2]*Q[1] + ^Q[2]*^Q[0] + Q[1]*^Q[0]
SEG[2] = Q[2] + ^Q[1] + Q[0]
SEG[1] = Q[3] + ^Q[2] + Q[1]*Q[0] + ^Q[1]*^Q[0]Implementation
Instantiation in SNL:
part=pla1 type=pla i=one,one,q[3:0] o=seg[7:1]Personalization via CLAMP commands (Product terms 1 to 12):
# AND Plane (4 Inputs * 12 Products)
# 1:Q3, 2:Q2, 3:Q2*^Q1, 4:Q2*^Q1*Q0, 5:Q2*^Q0, 6:^Q2*Q1, 7:^Q2*^Q0,
# 8:Q1, 9:Q1*Q0, 10:Q1*^Q0, 11:^Q1*^Q0, 12:Q0
CLAMP part=pla1 AND=4*12 BITMAP= $
1xxx x1xx x10x x101 x1x0 x01x x0x0 xx1x $
xx11 xx10 xx00 xxx1
# OR Plane (12 Products * 7 Outputs)
# Note the '0' for complemented connections to PT 8 (SEG[2]) and PT 2 (SEG[1]).
CLAMP part=pla1 OR=12*7 BITMAP= $
1x1x11xxxxxx 1xx1xx11xxxx 1x1x1xxxxx1x $
xxxxxx1xx1xx xxx1x11xx1xx x1xxxxx0xxx1 $
10xxxxxx1x1xX-Handling & Special States
- Chip Select (CS): If 0, all outputs are High-Z (floating). If X, all outputs are X.
- Enable (EN): If 0, all outputs are at the default value (configurable via
CLAMP ENABLE=). If X, all outputs are X. - Input Unknowns: If an input is X, product terms depending on it become X unless forced to 0 by another input.
- Internal Efficiency: Simic uses a packed bitmask internally to evaluate PLAs, making them extremely fast even for large matrices.