RAMB

Dual Port RAM primitive with independent read and write ports.

MEMORY

Model

Pin	Function
`CS`	Chip Select (Active High). If Low, outputs are High-Z and writes are disabled.
`RE`	Read Enable (Active High). Enables level-sensitive read from `RADDR`.
`WE`	Write Enable (Active High). Enables level-sensitive write from `DATAIN` to `WADDR`.
`RADDR`	Read Address input bus.
`WADDR`	Write Address input bus.
`DATAIN`	Data input bus for writes.
`DATA`	Data output bus for reads.

RAMB allows simultaneous read and write operations from different addresses.

Read: Level sensitive. Active when CS and RE are High. Reads from RADDR.
Write: Level sensitive. Active when CS and WE are High. Writes DATAIN to WADDR.

Conflict Handling: If the same address is simultaneously read and written, the output data is undefined (X).

RAMB contents are initialized pre-simulation using the DATA keyword in the PART statement, or the CLAMP command.

# Static initialization in netlist
PART=U1 TYPE=RAMB DATA=X0, 55, AA

# Dynamic population in run script
CLAMP PART=U1 DATA=X0 55 AA

For detailed information on the DATA syntax, X-handling behavior, and the CLAMP command, see the Memory Handling & Initialization guide.

Read Port: If RADDR contains X, the simulator checks all possible addresses. If data differs across matching locations, output is X.
Write Port: If WADDR contains X during an active write (CS=1, WE=1), all potential addresses identified by the X-mask are invalidated (set to X).
Conflicts: If RADDR == WADDR and a write occurs simultaneously with a read, the read output is forced to X.

Address Depth: Both RADDR and WADDR must have the same width (m+1 bits).
Data Width: DATAIN and DATA buses must have the same width (n+1 bits).
Port Independence: Read and Write ports operate asynchronously; however, simultaneous access to the same address is flagged as a conflict.

Type=RAMB i=CS,RE,WE,RADDR[m:0],WADDR[m:0],DATAIN[n:0] o=DATA[n:0]