Input Stimuli

Introduction

After the main type's compiled description has been loaded by the GET command, external stimuli must be defined and applied to its pins in order to exercise its functionality and verify its design. The stimuli are applied to the main type's input (unidirectional) and bus (bidirectional) pins. These ports are collectively called primary inputs (even though the busses will sometimes function as outputs, they must still be driven the remainder of the time from the external world), and the stimuli are called input stimuli.

SIMIC supports three different modes of simulation that are specific to the circuit's basic operation and the reasons for performing the simulation. The simulation mode is determined by the input stimuli:

1. Simulate-till-stable - selected by applying patterns, this enforces Fundamental Mode operation.
2. Time-based inputs - selected by applying waveforms, this mode supports arbitrary primary input timing.
3. Tester emulation - selected by applying timing generators, this mode supports tester program debugging.

Types Of Input Stimuli

SIMIC supports three different types of input stimuli:

Patterns

If applicable, this stimulus mode is extremely helpful in troubleshooting designs. For patterns, only the input values are specified, not their times of application. SIMIC applies each input pattern, simulates the circuit until its state becomes stable (internal activity ceases, and every element output state is consistent with its input and internal state), and only then applies the next input pattern. This mode of operation is also called Fundamental Mode, and many circuits are designed to operate exactly in this manner.

Patterns are useful for a number of reasons:

1. The circuit is guaranteed not to lose Fundamental Mode operation, since the effects of a subsequent input pattern cannot interact with events caused by the current pattern.
2. Simulation time is reset to 0 at the start of each pattern. Coupled with the option to output simulation results when the circuit state is stable, the circuit's response time for each input pattern is visible in the simulation output.
3. As a debugging aid, SIMIC always saves the state of the network at the previous stable point. Since a timing hazard must be caused by a single pattern, the user can interactively "replay" the hazard to obtain insights on the cause and ultimately the fix of the hazard. This dramatically reduces circuit debugging time. (Note that this is the only stimulus mode where the circuit is guaranteed to achieve stability for each input state; and therefore the only mode where the network state is guaranteed to be saved prior to any event of interest.)

>>: STEP ONE=done

Waveforms

For waveforms, both the input values and their times of application are specified. Each input state is then applied at its specified time, regardless of the stability of the circuit.

Waveforms should be used to test circuits whose input arrival times are unconstrained. These include asynchronous circuits, dynamic logic, frequency-sensitive circuits, retimers (e.g. UARTS), and non-synchronous pipelined architectures.

Timing Generators

Timing generator mode emulates modern automatic test equipment, thus allowing test programs to be debugged using simulation techniques. In this mode, stimuli are defined by input drive values, timing generators, and a master clock period, and outputs are strobed. The period, timing generator definitions and strobe placements may be dynamically changed during the simulation (time-set switching).

See Tester Emulation for a full description of timing generators.

Test Numbers

In order to maintain a consistent reference, SIMIC assigns a test number to each distinct input state. The first input state applied is Test 1, the second is Test 2, and so on. Test numbers are incremented as follows:

1. patterns - whenever a new pattern is applied. Also time is reset to 0
2. waveforms - whenever an input changes state
3. timing generators - whenever a new test period is entered; thus, the test number is equivalent to the tester period number.

Specifying Stimuli As A Two-Step Process

Input stimuli are specified in a two-step process. In the first step, the patterns, waveforms, or timing generators are specified with the DEFINE run command. Then these defined sequences are applied to the proper inputs with the APPLY command.

This two-step approach has the following advantages:

1. Stimuli may be defined hierarchically.
2. If the same sequence is to be applied to different inputs, then that sequence needs to be defined only once.
3. If more than one mode will be used to simulate the circuit, stimulus definitions in terms of patterns, waveforms, or timing generators can coexist without conflict, since only one type is applied for actual simulation.

Defining Input Stimuli

Primary input stimuli are defined using the DEFINE (DE) run command.

The syntax is:

DEFINE <pw><name>.<width><defaults> = <sequence>

where:

• <pw> is either a P (for patterns) or W (for waveforms),
• <name> is a user-defined name for the input sequence, immediately following the <pw> designator; combined, the two entries form the sequence's complete name,
• <width> is the number of signals for which the input sequence is defined,
• <defaults> (optional) specifies default attributes of the stimulus sequence appearing on the right side of the equal sign, and
• <sequence> is the stimulus sequence being defined.

The optional <defaults> on the left side of the equal sign are:

.<duration>.<format>.<strength>

where:

• <duration>, called the default duration, is
  • for patterns, the number of tests to maintain each input state of <sequence> before applying the next one. If unspecified, each input state is maintained for one test (the default duration is 1)
  • for waveforms, the amount of time to maintain each input state of <sequence> before applying the next one. If unspecified, the default duration is 0, which means that all stimulus timing must be described in <sequence>
• <format> is the default format (radix) of <sequence> (BINARY, OCTAL, HEXADECIMAL, INTEGER). If unspecified, the default is BINARY, and
• <strength> is the default strength of <sequence> (POWER, DRIVING, RESISTIVE, FLOATING). If unspecified, the default is DRIVING.

<format> and <strength> specifications may be abbreviated to any valid prefix, even one character. For example, HEXADECIMAL can be specified as: H, HE, HEX, HEXA, etc.

Note that a single dot (.) separates each pair of adjacent specifications on the left side of the equal sign.

Example 1: Simple Pattern Definition

>>: DEFINE PALL.3 = 000 001 010 011 100 101 110 111

This defines a pattern, since the <pw> character is P. The pattern's name is PALL, and its width specification, 3, is separated from the name by a dot (.). Since there are no <duration>, <format>, or <strength> specifications following the width entry, the default duration of each stimulus state is one test, the radix of <sequence> is BINARY, and the stimuli have DRIVING strength.

Example 2: Waveform Definition with Duration

The time-based stimuli shown in the following waveform diagram:

0 100 200 300 400

time-units

can be described as:

>>: DEFINE WSAMPLE.2.100 = 00 01 10 11

This statement specifies <pw> as W (a time-based waveform), <name> as SAMPLE (so the waveform's complete name is WSAMPLE), <width> as 2, and <duration> as 100. Since format and strength are not specified, the format is BINARY and the strength for each stimulus is DRIVING.

The names assigned to stimulus sequences must be unique. SIMIC does, however support stimulus redefinition; if a stimulus definition has the same name as a previously-read definition, it replaces the original one. The only restriction is that their <width>s must be identical.

Selecting Stimuli For Simulation

After a stimulus sequence is defined and named by the DEFINE command, it must be attached to the primary inputs/busses of the circuit. This is done with the APPLY (AP) PATTERN (PA) run command. The syntax of this command is:

APPLY PATTERNS=<pwname> LIST=<signals> BEGIN=<n>

where:

• <pwname> is the name assigned to the sequence by a preceding DEFINE command, beginning with P if the sequence is a pattern or with W if the sequence is a waveform,
• <signals> is a list of the primary input/bus pins to apply the stimuli to, and
• <n> is an offset (skew) from the current time or test for delaying application of the stimuli. If unspecified, the offset is 0.

The order of the primary signals in <signals> specifies the correspondence between bit positions in <pwname> and the signals. The first signal in <signals> will be associated with the first bit position in <pwname>, and so on.

Example: Applying Pattern PALL

>>: APPLY PATTERNS=PALL LIST=c,b,a

Associates the three-bit pattern named PALL with the three primary signals c, b, and a, in that order. These three signals will therefore execute the following sequence, where the duration of each state is one test:

TEST:  1   2   3   4   5   6   7   8
c:     0   0   0   0   1   1   1   1
b:     0   0   1   1   0   0   1   1
a:     0   1   0   1   0   1   0   1

Example: Applying Waveform WSAMPLE

>>: APPLY PATTERNS=WSAMPLE LIST=x,y

Associates the two-bit waveform named WSAMPLE with the two primary signals x and y, in that order. These two signals will therefore execute the following sequence, where the duration of each state will be 100 time-units:

TIME:  0     100   200   300
x:     0     0     1     1
y:     0     1     0     1

Omitting the LIST Keyword

If the stimulus width is equal to the total number of primary inputs and busses, and the pattern values are ordered as inputs followed by busses, and the input and bus values are themselves ordered as they appear in the circuit's main type statement, then the LIST (LI) keyword-field may be omitted.

For example, if the input keyword-field of the main type's TYPE statement is I=X,Y, and there are no primary busses, then the LIST=X,Y keyword-field in the above APPLY command is optional, since this would be the default association of primary inputs and stimuli.

Overriding Previous Assignments

Subsequent APPLY commands override previous APPLY commands for common primary signals. For example, if the command:

>>: APPLY PATTERNS=PAT1 LIST=a,b,c

is erroneously issued, and the intended pattern for these signals is PAT2, the subsequent command:

>>: APPLY PATTERNS=PAT2 LIST=a,b,c

overrides the previous error and applies PAT2. Primary input grouping need not be identical in APPLY commands. For example, if PAT3 has a width of 1, and if the command:

>>: APPLY PATTERNS=PAT3 LIST=c

is subsequently issued, then the first two bit positions of pattern PAT2 will be applied to inputs a and b, and PAT3 will be applied to input c.

The BEGIN Keyword

The BEGIN (BE) keyword is optional and is used for the following:

1. In waveforms, BEGIN can skew one waveform with respect to another. This simplifies testing the circuit's sensitivity to input skew.
2. The BEGIN option can also be used to apply "patches" (positioned stimuli) to the inputs in any mode. The patch is applied at the test (for patterns) or time (for waveforms) specified by the BEGIN keyword-field.

Validating Output Results

Overview

In addition to applying input stimuli, SIMIC allows you to specify expected output values and automatically validate that your circuit produces the correct results. This powerful feature works with both patterns and waveforms, enabling automated verification and regression testing.

Applying Expected Results

Expected results are applied to primary outputs and bidirectional busses using the APPLY EXPECTED command. The syntax mirrors the APPLY PATTERNS command:

APPLY EXPECTED=<pattern> LIST=<signals> BEGIN=<n>

where:

• <pattern> is a previously defined pattern name (must start with P)
• <signals> is a list of primary output or bidirectional bus signals
• <n> (optional) specifies the test or time when validation should begin

Example: Pattern Mode with Expected Results

>>: DEFINE PINPUTS.4.1.HEX = 0 1 2 3 4 5 6 7 8 9 A B C D E F
>>: DEFINE PEXPECT.8.1.HEX = 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E
>>:
>>: APPLY PATTERNS=PINPUTS LIST=in[0:3]
>>: APPLY EXPECTED=PEXPECT LIST=out[0:7]
>>:
>>: SIMULATE

In this example, SIMIC will check that out[0:7] matches the expected values when the circuit becomes stable after each input pattern. Any mismatch generates a warning message.

Example: Waveform Mode with Expected Results

>>: DEFINE WCLK.1.100 = 0 1 0 1 0 1 0 1
>>: DEFINE WDATA.8.100.HEX = 00 AA 55 FF 3C C3 0F F0
>>: DEFINE WEXPECT.8.100.HEX = XX 00 AA 55 FF 3C C3 0F
>>:
>>: APPLY PATTERNS=WCLK LIST=clock
>>: APPLY PATTERNS=WDATA LIST=data_in[0:7]
>>: APPLY EXPECTED=WEXPECT LIST=data_out[0:7]
>>:
>>: SIMULATE

Note the use of XX (don't care) in the first position of WEXPECT to ignore the initial output value. For waveforms, SIMIC checks expected values at each input state change.

Checking Behavior by Mode

SIMIC validates expected results differently depending on the simulation mode:

Controlling Validation Messages

By default, mismatches between expected and actual values generate warning messages. You can control this behavior using the WARN and BREAK commands:

Enable Warnings (Default)

WARN EXPECTED: LIST=<signal list>

Disable Warnings

NO WARN EXPECTED: LIST=<signal list>

Break on Mismatch

To halt simulation immediately when a mismatch occurs:

BREAK EXPECTED: LIST=<signal list>

Remove Breakpoint

NO BREAK EXPECTED: LIST=<signal list>

Don't Care Values

Use X in expected patterns to indicate "don't care" values. When the expected value is X, any actual output will be considered correct. This is useful for:

• Initial conditions where outputs are undefined
• Reset sequences
• Timing-dependent outputs
• Outputs that vary based on implementation details

Example with Don't Care Values

>>: DEFINE PRESET.1 = 1 0 0 0
>>: DEFINE PEXPECT.8.HEX = XX XX 00 55
>>:
>>: APPLY PATTERNS=PRESET LIST=reset
>>: APPLY EXPECTED=PEXPECT LIST=output[0:7]

The first two tests accept any output value (during reset), while tests 3 and 4 must produce specific results.

Practical Applications

1. Regression Testing

Capture correct behavior as expected patterns and automatically detect when changes break functionality:

>>: DEFINE PTEST.16 = ... comprehensive test vectors ...
>>: DEFINE PGOLDEN.16 = ... known good outputs ...
>>: APPLY PATTERNS=PTEST LIST=inputs[0:15]
>>: APPLY EXPECTED=PGOLDEN LIST=outputs[0:15]
>>: SIMULATE

2. Debugging with Breakpoints

Stop simulation at the exact point where output becomes incorrect:

>>: BREAK EXPECTED: LIST=critical_output
>>: SIMULATE
# Simulation stops at first mismatch for interactive debugging

3. Partial Validation

Check different output groups with different expected patterns:

>>: DEFINE PDATA_EXP.8 = ...
>>: DEFINE PSTAT_EXP.4 = ...
>>: APPLY EXPECTED=PDATA_EXP LIST=data_out[0:7]
>>: APPLY EXPECTED=PSTAT_EXP LIST=status[0:3]

Best Practices

• Start with warnings: Use default warning mode during development to see all mismatches
• Use breakpoints selectively: Apply BREAK EXPECTED only to critical outputs
• Leverage don't cares: Use X for outputs that shouldn't be checked
• Document expected values: Add comments explaining why specific values are expected
• Test incrementally: Validate small portions first, then expand coverage

DO Loops For Repetitive Sequences

Any repeating sequence (or subsequence) of stimulus states may be specified as a loop. The form of a loop is:

DO <count> (<sequence>)

where:

• <count> is the number of times to repeat the loop, and
• <sequence> is the sequence to be repeated.

Optional whitespace may precede or follow the repetition factor, <count>.

Loops can be nested within loops. There is no practical limit to the level of nesting.

Example

The command:

>>: DEFINE PR.1 = 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 1

defines a pattern sequence for one primary signal. Its default duration is one test. This sequence can also be expressed as:

>>: DEFINE PR.1 = DO 2 (0 1 0 1 1 1 1 1)

or as:

>>: DEFINE PR.1 = DO 2 ( DO 2 (0 1) DO 4 (1) )

or even as:

>>: DEFINE PR.1 = DO 2 ( DO 2 (0 1) DO 2 (DO 2 (1)) )

Grouping

Stimuli may be defined for subgroups of the primary signals, as desired, to facilitate stimulus definition. Inputs that would typically be partitioned are master clear and/or preset, clocks, and synchronous data lines. For each partition there must be an associated APPLY command.

For example, consider the eight pattern sequence, PALL:

>>: DEFINE PALL.3 = 000 001 010 011 100 101 110 111
>>: APPLY PATTERN=PALL LIST=c,b,a

Another way to define and apply this sequence is:

>>: DEFINE PCB.2.2 = 00 01 10 11
>>: DEFINE PA.1 = DO 4 (0 1)
>>: APPLY PATTERN=PCB LIST=c,b
>>: APPLY PATTERN=PA LIST=a

Here, pattern PCB is defined and applied to signals c and b, and pattern PA is defined and applied to signal a. Note that the default duration of PCB is 2, so this pattern's sequence is actually:

00 00 01 01 10 10 11 11

A third method of defining and applying these patterns is:

>>: DEFINE PC.1.4 = 0 1
>>: DEFINE PB.1.2 = DO 2 (0 1)
>>: DEFINE PA.1 = DO 4 (0 1)
>>: APPLY PATTERN=PC LIST=c
>>: APPLY PATTERN=PB LIST=b
>>: APPLY PATTERN=PA LIST=a

Note that patterns PC and PB are equivalent to:

>>: DEFINE PCEQUIV.1 = 0 0 0 0 1 1 1 1
>>: DEFINE PBEQUIV.1 = DO 2 (0 0 1 1)

Handling Unequal Group Lengths

If the applied groups do not all end at the same test, then the last stimulus value of each group will be maintained until all groups are finished. For example, suppose that circuit has two inputs, clock and reset, and the input sequence must:

1. Apply the reset signal, which is active-high.
2. Remove the reset.
3. Clock the device 64 times.

This could be accomplished by:

>>: DEFINE PRESET.1 = 1 0
>>: DEFINE PCLOCK.1 = 0 0 DO 64 (1 0)
>>: APPLY PA=PRESET LI=reset
>>: APPLY PA=PCLOCK LI=clock

in which the last 128 patterns of PRESET are omitted. During simulation, SIMIC will maintain the last value of PRESET, 0, while the DO loop of PCLOCK is being expanded.

Stimulus Hierarchy

Stimulus definitions may reference other stimulus definitions as long as the width of both definitions are the same. This is accomplished by placing the referenced sequence's name at the proper location in the sequence being defined. There is no practical limit on the level of nested stimulus definitions.

Example 1: Building Hierarchical Patterns

The pattern:

>>: DEFINE PCLOCK.1 = 0 0 DO 64 (1 0)

could also be defined as:

>>: DEFINE PFIRST2.1.2 = 0
>>: DEFINE PCYCLES.1 = DO 64 (1 0)
>>: DEFINE PCLOCK.1 = PFIRST2 PCYCLES

Here, pattern PCLOCK contains two subsequences, the first being PFIRST2 and the second PCYCLES. During simulation, SIMIC expands PCLOCK exactly in this order. PFIRST2 is expanded first; it consists of a single 0 level whose duration is two tests. After PFIRST2 is completed, expansion of PCYCLES begins (starting at Test 3).

Example 2: Alternative Hierarchical Definition

An alternative hierarchical definition of PCLOCK might be:

>>: DEFINE PCYCLES.1 = 1 0
>>: DEFINE PCLOCK.1 = 0 0 DO 64 (PCYCLES)

Primitive Values vs. Hierarchical References

Sequence entries that directly represent logic levels (e.g., 0, 1) are called primitive values. Thus, every sequence definition may contain a mixture of primitive values and hierarchical references. In general, a hierarchical reference can be placed wherever a primitive value can be placed.

Thus, the DEFINE command of the last example above could have been:

>>: DEFINE PCLOCK.1.2 = 0 DO 64 (PCYCLES)

Here, the default duration of 2 only applies to the primitive value 0. The default duration of primitive values in PCYCLES is determined by its DEFINE command.

Stimulus Drive Strength

If a primary input is only connected to inputs of unidirectional elements, then its drive strength is not very important. The drive strength of an external source connected to a primary bus, however, may be crucial for proper operation. A primary bus can be driven either by an external source or by a driver inside the circuit being simulated. Sometimes, it may be driven by both sources simultaneously, whether by design (e.g., a strong reset) or by error (e.g., a data bus that should have at most one driver at any time).

Thus, it is sometimes necessary to specify the drive strength of primary stimuli. The DEFINE command's default <strength> option specifies the drive strength of primitive values in the sequence being defined. One of four strengths may be specified, corresponding to the supported drive strengths for gate-level components:

• POWER
• DRIVING
• RESISTIVE
• FLOATING

Any prefix of these strength designations is a valid specification. If this option is unspecified, the default drive strength is DRIVING.

Strength Override by Primitive Values

The default strength specification does not affect all primitive values. Some primitive values have an associated strength as well as level, and the associated strength prevails over the default strength specification. For example, the primitive entry Z (or z) represents "unknown level at floating strength". The DEFINE commands:

>>: DEFINE WSEQ_D.1.50 = 0 1 X Z
>>: DEFINE WSEQ_R.1.50.R = 0 1 X Z

both define a sequence of values consisting of 0 for 50 time-units, 1 for 50 time-units, X (representing "unknown; either 0 or 1") for 50 time-units, and Z. Since no default strength is specified for WSEQ_D, its 0, 1, and X values will be applied at DRIVING strength. Since a default strength of R is specified for WSEQ_R, its 0, 1, and X values will be applied at RESISTIVE strength. The last state of both sequences will be the same floating-unknown value, Z.

Combined Level/Strength Symbols

In addition to Z, other primitive value symbols represent drive strengths as well as binary logic levels. These are also the symbols that SIMIC uses to report signal states. The table below shows these symbols and the combined level/strength values they represent:

Stimulus Format

Default Format Specification

The DEFINE command's default <format> option specifies the default format of primitive values in the sequence being defined. One of four formats may be specified:

• BINARY
• OCTAL
• HEXADECIMAL
• INTEGER

Any prefix of these format designations is a valid specification. If this option is unspecified, the default format is BINARY.

Format Descriptions

The following summarizes the primitive values representing stimulus levels for each format:

BINARY FORMAT

Each stimulus state, consisting of <width> levels, is represented as <width> binary levels. Logic levels 0 and 1 are represented by the identical symbols, 0 and 1. (Additionally, nine symbols are used to represent combined level/strength states; see Stimulus Drive Strength.)

OCTAL FORMAT

Each stimulus state, consisting of <width> levels, is represented as a right-justified octal number. Levels 000 through 111 are represented by the corresponding octal symbols 0 through 7.

HEXADECIMAL FORMAT

Each stimulus state, consisting of <width> levels, is represented as a right-justified hexadecimal number. Levels 0000 through 1111 are represented by the corresponding hexadecimal symbols 0 through F (or f).

INTEGER FORMAT

Each stimulus state, consisting of <width> levels, is represented as either a positive or negative integer. The integers represent the binary number formed when the leftmost level is used as the most significant bit. Negative integers specify the 2's complement binary representation.

The only format restricted in size is INTEGER. This format can represent, at most, 32 signal levels. There are no restrictions for the other formats.

Common Symbols for All Formats

Additionally, some symbols are used for all formats. They specify values for a group of signals, where the group is:

• a single signal for binary format
• all signals of an octal digit for octal format
• all signals of hexadecimal digit for hexadecimal format
• all <width> signals of the stimulus sequence for integer format

These common symbols are:

• X - specifies that all signals of the group are X (could be either 0 or 1)
• Z - specifies that all signals of the group have floating unknown values (this is the only primitive value that also specifies drive strength for all formats)
• I - specifies that all signals of the group be generated by inverting (bitwise complementation) their previous levels
• N - specifies that all signals of the group be generated by copying their previous levels

Example: Equivalent Format Definitions

The following DEFINE commands are equivalent:

>>: DEFINE PABC.5 = 00000 11111 01101 ZZZZZ XXXXX
>>: DEFINE PABC.5 = 00000 IIIII INNIN ZZZZZ XXXXX
>>: DEFINE PABC.5.OCT = 00 37 15 ZZ XX
>>: DEFINE PABC.5.OCT = 00 I7 15 ZZ XX
>>: DEFINE PABC.5.HEX = 00 1F 0D ZZ XX
>>: DEFINE PABC.5.HEX = 00 1F ID ZZ XX
>>: DEFINE PABC.5.INT = 0 31 13 Z X
>>: DEFINE PABC.5.INT = 0 -1 13 Z X
>>: DEFINE PABC.5.INT = 0 I 13 Z X

Radix Escapes

The radix may be explicitly switched for specific input states of the stimulus definition. This is done by prefixing each input state with a radix escape character from the table below:

Each radix escape character only affects a single input state.

Example: Using Radix Escapes

Radix escape is useful when signals grouped within a digit must be assigned incompatible values. For example:

>>: DEFINE PBUS.4.HEX = 0 ^01XX %-1 Z *0Z

defines the following patterns:

0000 01XX 1111 ZZZZ 0ZZZ

Here, the second and fifth input states could not be specified in hexadecimal format, since X or Z would set all four bits to the respective values.

Example: Mixed Radix for ALU Testing

Changing radix may also facilitate stimulus description. For example, suppose an 8-bit ALU performs arithmetic operations on its data inputs, a and b, when its 2-bit control input, func, is 0 or 1, and logical operations on the inputs when func is 2 or 3. Stimulus description would be simplified if the data inputs were specified as integers for the arithmetic operations and as hexadecimal (or binary or octal) for the logical operations. For example:

>>: DEFINE PFUNC.2.INT = 0 1 2 3
>>: DEFINE PA.8.INT = -2 255 #0F #50
>>: DEFINE PB.8.INT = 1 255 #F5 #0A

Guidelines for Entering Proper Values

The following guidelines should be followed for specifying stimulus values:

1. For binary, octal, and hexadecimal formats:

• exactly the right number of digits must be used to represent each stimulus state value
• spacing between different stimulus state values is optional, but a space should not appear within (break up) a stimulus state value for octal and hexadecimal formats

2. For integer formats:

• whitespace or commas must appear between stimulus state values

3. For all formats:

• the value specified for each stimulus state must be consistent with the number of primary signals in the sequence

4. Radix escapes:

• must specify a complete stimulus state value (i.e., specify the values of all primary signals associated with the stimulus)

Simply stated, (1a) specifies that leading zeros of octal and hexadecimal digits cannot be omitted, and no extra digits can be added to a stimulus state specification, since the extra digits will be interpreted as belonging to the next stimulus state. The latter possibility is due to (1b), which states that stimulus specification for these radices is format-free between state values.

More formally, (1a) requires that each stimulus state specification consist of exactly

ceiling(<width> / log₂(radix))

digits, where the ceiling function is "the smallest integer greater than, or equal to, its argument", and radix is 2, 8, or 16 for BINARY, OCTAL, or HEXADECIMAL formats, respectively. Thus, the correct number of digits per stimulus state value specification must be <width>, ceiling(<width>/3), or ceiling(<width>/4), respectively, for the three formats.

Guideline (2) is fairly obvious; since integers can contain a varying number of digits, something has to delimit them.

Guideline (3) states that the stimulus state value cannot exceed (2^<width>-1 - 1).

For negative integers, this value cannot be less than (-2^<width>-1).

Any value specified outside these limits is out of range for the given number of primary signals. If the correct number of digits are used, but the specified value is out of range, SIMIC discards the extraneous most-significant bits, issues a warning message, and accepts the truncated value.

Guideline (4) states that, within a single stimulus state, it is an error to define some primary signals in one radix and the remaining signals in another radix.

Stimulus Positioning

In addition to the default duration option, <duration>, on the left side of the DEFINE command, stimulus states may be positioned using two constructs on the right side (within the sequence being defined). These constructs are absolute positions and explicit durations. They eliminate the need to repeat levels that remain constant for long intervals, and allow positioning at points that are not multiples of the default duration.

To demonstrate the features of positioning, the sequence of patterns PALL will be used:

TEST:  1   2   3   4   5   6   7   8
c:     0   0   0   0   1   1   1   1
b:     0   0   1   1   0   0   1   1
a:     0   1   0   1   0   1   0   1

The patterns for a, b, and c can be defined separately as:

>>: DEFINE PA.1 = 0 1 0 1 0 1 0 1
>>: DEFINE PB.1 = 0 0 1 1 0 0 1 1
>>: DEFINE PC.1 = 0 0 0 0 1 1 1 1

Default Positioning

Briefly reviewing, a default duration, <duration>, can be specified in the definition of a stimulus sequence. If unspecified, the default duration is implicitly 1 for patterns and 0 for waveforms. Using default durations, the pattern definitions for b and c can be simplified:

>>: DEFINE PB.1.2 = 0 1 0 1
>>: DEFINE PC.1.4 = 0 1

As can be seen, the default duration simplifies description when a stimulus sequence contains periodic changes. However, repetitive levels must still be entered for nonperiodic changes:

>>: DEFINE WX.1.10 = 0 1 0 0 1 1 0 0 0 1 1 1 0

Absolute Positioning

Absolute positioning places a primitive value, DO loop, or hierarchical reference at an absolute position with respect to the beginning of the sequence. Absolute positioning is specified as an at-sign (@) followed by a position value. The immediately following primitive value, DO loop, or hierarchical reference will be placed at the specified position.

Using absolute positioning, the definitions for b and c might be:

>>: DEFINE PB.1 = 0 @3 1 @5 0 @7 1
>>: DEFINE PC.1 = 0 @5 1

This definition of PB places a 0 at Test 1, a 1 at Test 3, a 0 at Test 5, and a 1 at Test 7. Similarly, the definition of PC places a 0 at Test 1 and a 1 at Test 5.

Similarly, the definition of WX using absolute positioning could be:

>>: DEFINE WX.1.10 = 0 1 0 @40 1 @60 0 @90 1 @120 0

As mentioned above, absolute positioning is relative to the start of the sequence. If the sequence is within a DO loop, then the most immediate left parenthesis marks the sequence's start. For example, in:

>>: DEFINE PY.1 = 0 @5 DO 2 (1 @3 0)

the absolute position specification, @3, is with respect to the left parenthesis, not the beginning of the entire sequence (which @5 references). This definition expands to:

0000 110 110

Explicit Duration

Explicit durations specify how long to hold the previous stimulus state, prior to initiating the next one. The previous state might have resulted from a primitive value within the current definition or from a hierarchical reference. Explicit duration is specified as an ampersand (&) followed by the duration value. The previous stimulus state will be held for the specified duration.

Again, b and c could be defined in terms of explicit durations as:

>>: DEFINE PB.1 = 0 &2 1 &2 0 &2 1
>>: DEFINE PC.1 = 0 &4 1

Here, in PB, 0 is placed at Test 1 and held for 2 tests, then 1 is placed and held for 2 tests, etc. Similarly, the 0 in PC is held for 4 tests until the 1 is applied at Test 5.

Positioning Precedence

The positioning methods described above may be freely mixed. The rule is: "do whatever is easiest". If there is a conflict between positioning specifications, SIMIC resolves them by the following order of precedence (highest to lowest):

1. Absolute positioning (@ specification).
2. Explicit duration (& specification).
3. Default duration (<duration> specification).

Summary

SIMIC provides three powerful types of input stimuli to support different verification needs. Patterns enforce Fundamental Mode operation and provide automatic timing analysis ideal for synchronous designs. Waveforms offer complete timing control for asynchronous circuits and timing-sensitive designs. Timing generators emulate test equipment for manufacturing test program development.

The two-step DEFINE/APPLY process enables stimulus reuse, hierarchical definitions, and flexible test development. Combined with features like DO loops, grouping, radix escapes, and positioning controls, SIMIC's stimulus system provides the flexibility needed for comprehensive circuit verification.

Validating Results: In addition to defining input stimuli, SIMIC supports APPLY EXPECTED for specifying expected output values. This powerful feature automatically compares simulation results against expected values and generates warnings or breakpoints on mismatches, enabling automated regression testing and design validation across all three stimulus modes.

For detailed information on tester emulation mode, including timing generators, drive masks, enable masks, and strobes, see Tester Emulation. For complete documentation on expected results validation, see the Expected Results Validation section.