Signal Behavior

Signal decay, spike propagation, wire-ties, and multi-driver dominance.

Introduction

Beyond basic timing, SIMIC models advanced signal behavior including decay to high-impedance states, spike filtering, and wire-tie resolution for multi-driver scenarios. These features enable accurate modeling of dynamic circuits, tri-state buses, and switch-level designs.

Signal Decay

When tri-state drivers enter high-impedance mode, the driven signals can decay to an unknown state over time. SIMIC models this behavior with signal decay specifications.

Decay Keywords

ODECAY (ODEC) - Output decay time
BDECAY (BDEC) - Bus decay time

Example: Tri-State Buffer with Decay

p=tbuf t=tpadn i=enable,data o=bus odel=5 odecay=20

When enable goes low, the driver enters hi-Z. After 20 time-units, bus transitions to unknown (X) unless another driver takes over.

Decay at Runtime

Modify decay values during simulation:

>>: set part=tbuf odecay=50
>>: simulate

Modeling Charge Storage: Use longer decay times to model capacitive charge storage. Use shorter times for resistive pull-ups/downs or when modeling worst-case leakage.

Wire-Ties and Multi-Driver Resolution

Wire-ties occur when multiple outputs or busses share the same signal name. SIMIC resolves conflicts based on specified dominance rules and drive strengths.

Types of Wire-Ties

Wired-AND (0-dominance) - If any strong driver outputs 0, the signal is 0
Wired-OR (1-dominance) - If any strong driver outputs 1, the signal is 1
CONFLICT (X-dominance) - If strongest drivers conflict or any is X, signal is X (default)

Example: Wired-OR Bus

* Tri-state buffers on shared bus (wired-OR):
p=p1 t=tpadn i=en1,dat1 o=bus odom=1
p=p2 t=tpadn i=en2,dat2 o=bus odom=1

With odom=1, if either driver outputs 1 while the other is hi-Z or also 1, the bus is 1. Only when all drivers are 0 or hi-Z does the bus go to 0 or decay.

Dominance Keywords

ODOM - Output dominance (values: 0, 1, X)
BDOM - Bus dominance (values: 0, 1, X)

Specification Rules:

Default dominance is X (CONFLICT) if unspecified
Dominance can be specified in any driver's PART statement
If specified multiple times, all specifications must be identical

Drive Strength

In wire-tie conflicts, SIMIC compares drive strengths to determine which drivers dominate. Stronger drivers override weaker ones.

Specifying Drive Strength

Use ODRIVE (outputs) or BDRIVE (busses) keywords:

* Strong driver:
p=strong_drv t=driver o=sig odrive=10

* Weak pull-up:
p=weak_pu t=resistor o=sig odrive=1

In a conflict, the driver with odrive=10 dominates over odrive=1.

Default Drive Strength

If unspecified, drive strength defaults to 5 (medium strength).

Conflict Thresholds

For fine-grained control, specify voltage thresholds for conflict resolution:

p=cmos_inv t=inv o=sig odom=[30,70]

In conflicts, if the combined drive results in voltage <30% of VDD, output is 0. If >70%, output is 1. Between 30-70%, output is X.

Spike Propagation Control

SIMIC can model inertial delay behavior where narrow input glitches may not propagate to outputs. This is controlled via FILTER and LIBERAL parameters.

Filter Parameter

Specifies the minimum pulse width (as % of output delay) that propagates. Narrower pulses are filtered.

Liberal Parameter

Specifies tolerance for X-propagation start time. Higher values delay X propagation, modeling inertia.

Example: Spike Filtering

p=and1 t=and i=a,b o=c odel=del1 ofilter=10% oliberal=30%

Pulses narrower than 10% of the delay are filtered. X-propagation starts 30% later than the pessimistic case, potentially filtering transient unknowns.

Filter Keywords

OFILTER - Output filter (percentage or absolute time)
BFILTER - Bus filter
OLIBERAL - Output liberal parameter
BLIBERAL - Bus liberal parameter

Disabling Spike Propagation: For pure functional verification (ignoring timing), use the run command: >>: no xpropagate spike

Input High-Impedance Defaults

By default, unconnected or high-impedance inputs are treated as unknown (X). This can be changed to model pull-ups, pull-downs, or floating inputs with predictable behavior.

HIZ Keyword

Specify default behavior for hi-Z inputs:

* Inputs default to logical-1 (pull-up):
t=my_logic i=a,b,c o=z hiz=1

* Inputs default to logical-0 (pull-down):
t=inverter i=in o=out hiz=0

Without hiz specification, hi-Z inputs default to X (unknown).

Practical Scenarios

Tri-State Bus Design

* Multiple devices sharing a tri-state bus:
type=bus_system i=clk,addr[7:0] b=data[7:0]

p=cpu t=processor o=data bdom=x bdecay=50
p=mem t=memory b=data bdom=x bdecay=50
p=io t=peripheral b=data bdom=x bdecay=50

Dynamic Logic with Decay

* Precharge/evaluate circuit:
p=precharge t=pmos i=phi,vdd o=node odecay=100
p=evaluate t=nmos_tree i=phi,a,b,c o=node

Wired-OR Open-Drain Bus

* I2C-style open-drain with pull-up:
p=pullup t=resistor o=scl odrive=1 odom=1
p=dev1 t=open_drain i=clk1 o=scl odom=1
p=dev2 t=open_drain i=clk2 o=scl odom=1