Advanced Delay Modeling

Specifying Decays In SNL

Decay characteristics are specified in PART or TYPE statement with the BUS-DECAY (BDEC) keyword-field for busses or the OUTPUT-DECAY (ODEC) keyword-field for outputs. The specified values for these key-words have a one-to-one correspondence with the busses and outputs, respectively. The decay values that can be specified are:

1. a positive number specifying the decay time
2. the name of a global delay
3. the reserved word INFINITE, or any prefix of this word.

The first and third options are self-explanatory. The second option, specifying a global delay, allows the decay time to depend on loading (capacitance). Since delay characteristics specify two delays, rise and fall, the node’s decay time is taken as the average value of the two delays for the given node capacitance. Generally, it is easiest to represent load-dependent decays by creating special global delays that contain the CHANGE keyword-field.

For example, the TPADN, a built-in primitive, is a tristating element with two inputs, EN (enable) and D (data). When EN is logical-1, the output is equal to the data input, and when EN is logical-0, the output tristates. Given the PART statement:

p=tri t=tpadn i=enable,data5 o=out5 odec=del83

suppose that, for the capacitance at the net named out5, the rise and fall delays for the delay characteristic del83 are 90 and 110, respectively, Then the decay time for this net will be their average value, 100.

Note: if different decay times are specified for a signal that has multiple drivers (wire-tie), then the signal’s decay will be the minimum value specified for any of its drivers.

Modifying Decays At Run Time

The SET DECAY command can be used to modify decays at run time. The DECAY keyword supports the same three options as the SET command’s delay modification keywords, plus a fourth option, setting infinite decay:

1. <n> - set decay to the specified value, <n> (an integer)
2. +<p>% or −<p>% - increase or decrease decay by the specified percent-age, <p> (an integer). (Note: the + sign is optional)
3. * - restore original decay from SNL description
4. INFINITE - set decay to infinite (any prefix of this word is valid)

The LIST keyword specifies the signals to be affected by the selected option. For example:

SET DECAY=infinite LIST=a,b

sets the decays of the two signals to infinite.

Functional Timing Checks

Timing checks are supported for the DNL and DPL (DL) latch and the DNCF, DPCF (DCF), JKNCF (JKCF), JKPCF, TNCF (TCF), and TPCF edge-triggered flip-flops. These checks can be specified within a TIMING-CHECKS block in any PART statement instantiating these built-in primitives.

In the following description, the active clock edge is the clock transition that causes the latch or flip-flop output to change state. This edge is the rising clock transition for the DPL (DL), DPCF (DCF), JKPCF, and TPCF primitives, and the falling clock transition for the DNL, DNCF, JKNCF (JKCF), and TNCF (TCF) primitives.

The supported timing checks are:

1. SETUP – this check specifies the minimum duration that an input must be stable prior to an active clock edge:

- DNL, DPL, DNCF, DPCF – setup from D (SETUP.D)

- JKNCF, JKPCF – setup from J (SETUP.J) and setup from K (SETUP.K)

- Additionally, all eight primitives support setup from reset (SETUP.NR), and setup from set (SETUP.NS). These setup times represent the minimum duration that the reset (set) must be inactive to reliably set (reset) the memory element via clock

2. HOLD – this check specifies the minimum duration that an input must be stable after an active clock edge:

- DNL, DPL, DNCF, DPCF – hold to D (HOLD.D)

- JKNCF, JKPCF – hold to J (HOLD.J) and hold to K (HOLD.K)

- Additionally, all eight primitives support hold to reset (HOLD.NR), and hold to set (HOLD.NS)

3. PULSE-WIDTHS – this check specifies the minimum width of a pulse on the set, reset, or clock lines. All eight primitives support: pulse-width reset (PW.NR), pulse-width set (PW.NS), and high and low pulse-width clock (PW.C.H and PW.C.L respectively).

The setup and hold checks for the asynchronous, active-low, set and reset inputs of all eight primitives are associated with the time duration between the rising (trailing) edge of pulses on these inputs and the active clock edge.

Unspecified timing checks default to 0 (disabled).

The syntax of a TIMING-CHECKS block is:

TIMING-CHECKS=begin; <spec>; …;<spec>; end;

where <spec> is a timing specification of the form <timing-check> = <limit>

Referencing a timing check by itself, without a qualifying pin name or clock level—SETUP, HOLD, PW—specifies all checks of that type. For example, in a TIMING-CHECKS block for a JKCF instance, SETUP specifies all setup checks; SETUP.J, SETUP.K., SETUP.NR, and SETUP.NS. Values specified for qualified timing checks supercede those specified for unqualified checks.

As an example, the timing block:

part=FF1 type=DCF i=reset,set,clk,data o=q1 $
    timing-checks= $
    BEGIN; $
    SETUP = 5; $
    HOLD.D = 10; $
    HOLD = 5; $
    PW = 4; $
    PW.C.L = 3; $
    END;

specifies:

1. All setups are 5 units.
2. All holds are 5 units, except hold from D which is 10.
3. All pulse-widths are 4, except clock-low pulse-width is 3.

Delay vs. loading curves, as well as MINIMUM, TYPICAL, and MAXIMUM delay sets can be used for specifying <limit>. If delay curves are used, then the loading on the part’s output is used to determine the timing check value. The syntax is identical to specifying local delays. For example:

timing-checks= $
    BEGIN; $
    SETUP = 25;20; $=maximum delay same as typical
    HOLD = [4,2];[3,1];[5,3]; $
    PW = (5,1)(7,3);4;[9,3]; $
    END;

Controlling Spike Propagation

Section Combinational Timing Hazards describes the spike hazard, a timing problem characterized by a sequence of changes at an element’s inputs such that an element output begins responding to the first input state, but before its response time elapses, a second input change occurs, causing the output to return to its original value. This situation is illustrated in Figure 23 for a two-input AND gate.

Figure 23 - Spike Hazard At An AND Gate

In this figure, the rise at signal A would normally cause output C to rise at time

t1 = tA + Tr

However, at time tB < t1, signal B executes a transition to 0, which forces signal C to be 0 at, or before, time

t2 = tB + Tf.

What value or values should signal C be assigned in the interval between tB and t2?

Since propagation delays are inertial, i.e., associated with charging and dis-charging node capacitance, and since, by assumption, the time required to charge signal C to the logic-1 threshold is Tr, one possible answer to this question is to maintain C at a constant 0, since the peak voltage level it reaches at time tB must be less than this threshold. This model, which ignores (filters out) the effects of transient input states whose duration is less than the output’s response time, is called inertial filtering.

Alternatively, since simulation is usually performed to predict the circuit’s operation in the real world, and since actual input arrival times, gate delays, and wiring delays will almost certainly differ from simulated values (the operation of circuits from separate production lots will also differ), it is very possible that an output pulse that almost happened during simulation will actually happen on some manufactured chips. Thus, another possible

answer to the above question, based on a conservative approach, is to set the value of signal C to X within this interval, since actual operation may be indeterminate at the time of simulation. This model, which creates an X-pulse when a spike hazard is detected, and propagates this pulse to all fanouts, is called spike propagation.

SNL supports flexible per-node control on the degree of pessimism introduced into spike propagation. The SIMIC XPROPAGATE run command provides the same control at run time (see Section 2.6.18 Enabling And Disabling X-Propagation).

Two parameters may be specified in any PART or TYPE statement to control spike propagation at each output:

1. filter – specifies a transient width threshold. Spike-producing transient input states that are narrower than this threshold will be inertially filtered, while transients at least as wide as the threshold will be propagated as X-pulses, if possible (the transient may still be filtered because of large differences between rise and fall delays; see below).

2. liberal – controls when to start the X-pulse. An X-pulse always ends at the time that the affected signal in guaranteed to have reached its known final value.

The filter threshold is expressed as percentage of the output’s response time. Thus, in the above example, if this threshold is 10%, then the spike will be inertially filtered if the difference in arrival times of the events at A and B, t B – tA, is less than 0.1×Tr. This value is specified as an integer between 0 and 100, inclusive, optionally followed by a percent (%) sign.

The value filter=0 introduces the greatest pessimism, since any input transient is at least as wide as this threshold. The value filter=100 introduces no pessimism, since all input transients are inertially filtered (this threshold corresponds to an input whose duration is the response time; but this is not a spike situation since the output has exactly enough time to respond).

The liberal value linearly controls the start of the X-pulse between the extremes of (a) the time of the input event causing the spike and (b) the time that the output would have responded to the first event. In the above example, these extremes are tB and t1. Adopting this notation to describe the general case, the X-pulse starts at time

tstart = tB + ×(t1 – tB)

where is the liberal value expressed as a decimal fraction from 0 to 1. The liberal values is specified as an integer between 0 and 100, inclusive, optionally followed by a percent (%) sign.

The value liberal=0 introduces the greatest pessimism, since it starts the X-pulse at tB, the time that the spike hazard is detected. The value

liberal=100 introduces the least pessimism, since it starts the X-pulse at t1.

Note that when an output’s rise and fall delays differ sufficiently, its response to the second input event can be earlier than its response to the first event. Using the notation of the above example, t2 may be earlier than t1 if Tf is sufficiently small. Since the X-pulse always ends at t 2, and since it is

possible to specify a liberal values that bring tstart close to t1, it is there-fore possible to specify a starting time for the X-pulse that is later than its

ending time. If this situation occurs, the X-pulse is not generated, and the transient input state is effectively inertially filtered.

The SNL keywords that specify the filter parameter are BUS-FILTER (BFILTER) for busses and OUTPUT-FILTER (OFILTER) for outputs. Similarly, the SNL keywords that specify the liberal parameter are BUS-LIBERAL (BLIBERAL) for busses and OUTPUT-LIBERAL (OLIBERAL) for outputs.

Unspecified values for any of these keyword options are defaulted to 0, the most pessimistic settings. To globally disable spike propagation when verifying logical correctness rather than timing, use the

NO XPROPAGATE SPIKE:

command (see Enabling And Disabling X-Propagation in Circuit Troubleshooting).

As an example, the PART statement

p=p15 t=xyz i=a,b,c o=d,e,f $ odel=dela,delb,delc ofilter=10%,,50 $ oliberal=30,20%

assigns:

output D a filter value of 10% and a liberal value of 30% output E a filter value of 0 and a liberal value of 20% output F a filter value of 50% and a liberal value of 0

Wire-Tie Dominance

If, in Figure 24, only one of the TPADN elements drives sig (the other being disabled with its enable input at logical-0), or if both elements drive the same level, then the value at sig is well-defined. If the elements simultaneously drive different values, then a conflict exists, and the resulting value at sig depends on the specified wire-tie characteristics. SIMIC sup-ports three types of wire-ties:

1. Wired-AND (0-dominance) – if any of the strongest components connected to the wire-tie is driving a logical-0, then the signal’s value is 0

2. Wired-OR (1-dominance) – if any of the strongest components connected to the wire-tie is driving a logical-1, then the signal’s value is 1.

3. CONFLICT (X-dominance) – if either (a) the state of at least one of the strongest drivers connected to the wire-tie is unknown, or (b) one or more of the strongest drivers is driving logical-0, while one or more of the remaining strongest drivers is simultaneously driving logical-1, then the signal’s value is undefined (set to X).

A wire-tie’s dominance can be specified in a PART or TYPE statement with the BUS-DOMINANCE (BDOM) keyword-field for busses or the OUTPUT-DOMINANCE (ODOM) keyword-field for outputs. These keywords associate in a one-to-one correspondence with the PART or TYPE statement’s busses and outputs, respectively. The values expected for these keywords are the

dominance categories 0, 1, or X.

For example, assume that a part has three outputs, each tied to other signals (but not to each other). If the wire-tie associated with the first output functions as a wired-AND, the wire-tie associated with the second output functions as a CONFLICT tie, and the wire-tie associated with the third output functions as a wired-OR, then ODOM=0,,1 should be specified in the PART statement.

If the dominance is unspecified, the default wire-tie type is CONFLICT (ODOM=X). Thus, wire-tie dominance only requires specification at wire-tied signals whose mutual interaction functions as a wired-AND or wired-OR.

A wire-tie’s dominance can be specified in any PART or TYPE statement associated with the common signal. If specified for more than one driver, the specifications must be identical.

For example, in the circuit of Figure 24, neither PART statement specifies a dominance for signal sig, so by default, the wire-tie is X-dominant. Placing an output dominance specification in either PART statement, or in both, specifies the wire-tie’s dominance, even if other drivers are connected to sig. If placed in multiple statements, all dominance specifications must be identical.

Sometimes, especially when functions are described at the switch level, a CONFLICT tie can generate a known result when an uncertain value would be more appropriate. This can occur during fault simulation, when a fault introduces a conflict that should not happen in the non-faulted circuit, or during circuit debugging, when a design error causes pullup and pulldown paths to conduct simultaneously.

For example, consider a CMOS inverter, where the P-device has a 5% greater ON-resistance than the N-device. If a fault puts the P and N devices in conflict, then the inverter’s output voltage would be approximately 0.49×VDD, not a logical-0 or logical-1. However since the N-device has a smaller ON-resistance, a CONFLICT tie would resolve the result to be a logical-0., and the fault might erroneously be classified as detected. Perhaps it would be more appropriate if the output value were unknown for this case.

The ODOM keyword also supports specification of logical-0 and logical-1 thresholds for wire-tie conflicts. Thresholds represent percentages of the full output voltage swing; they are specified as a pair of integers between 0 and 100 inclusive, enclosed within square brackets:

ODOM = [T0,T1]

where T0 is the logical-0 threshold, T1 is the logical-1 threshold, and T0 < T1.

When thresholds have been specified with the ODOM keyword, SIMIC treats the series depths of the ON switches as equivalent resistances and calculates the “voltage divider” ratio:

Sn / (Sn + Sp)

where Sn is the series depth of the pulldown path and Sp is the series depth of the pullup path. It then resolves the wire-tie conflict as follows::

- If this ratio is less than T0, or equal to T0 and T0 < T1, the output is set to logical-0.

- If this ratio is greater than T1, or equal to T1 and T0 < T1, the output is set to logical-1.

- Otherwise the output is set to X.

If the dominance of the CMOS inverter output in the above example had been assigned, say, the value ODOM=[30,70], then since 0.3 < 0.49 < 0.7, the inverter output in the faulted circuit would have been assigned the value X. The output value would only have been resolved as logical-0 if the series depth ratio were 0.3 or less. This would require the P device’s ON resistance to be at least 2.33 times the N device’s ON resistance:

Sn / (Sn + Sp) > 0.3 or 0.7×Sn < 0.3×Sp or 2.33×Sn < Sp

As special cases, the threshold specification [0,0] is equivalent to a wired-AND, [100,100] is equivalent to a wired-OR, and [50,50] is equivalent to a CONFLICT tie.

Specifying Drive Strength

Most wire-tied configurations are designed to have at most one active driver at any one time (e.g., address and data lines between a CPU, ROM, and RAM). Sometimes, however, correct operation requires that a strong driver overpower a weaker one. For these situations, it is necessary to incorporate drive strength into driver models.

Drive strength can be specified in any PART or TYPE statement. This value can be one of the following reserved words:

POWER, DRIVING, RESISTIVE, FLOATING.

Any prefix of these words is valid.

High (pullup) and low (pulldown) drive strengths may be specified independently, or simultaneously if identical. The associated keywords are:

BUS-DRIVE (BDRIVE) – high and low drive strength for busses BUS-LDRIVE (BLDRIVE) – low drive strength for busses BUS-HDRIVE (BHDRiVE) – high drive strength for busses OUTPUT-DRIVE (ODRIVE) – high and low drive strength for

outputs

OUTPUT-LDRIVE (OLDRIVE) – low drive strength for outputs OUTPUT-HDRIVE (OHDRiVE) – high drive strength for outputs

If a signal’s high or low drive strength is unspecified, the default strength is DRIVING.

For example, the PART statement:

P=p22 T=xyz I=a,b,c B=d,e O=f,g BHDRIVE=,res BLDRIVE=fl,pow ODRIVE=pow,res

assigns the following drive strengths:

bus D – high-drive=DRIVING, low-drive=FLOATING
bus E – high-drive=RESISTIVE, low-drive=POWER
output F – high-drive=low-drive=POWER
output G – high-drive=low-drive=RESISTIVE

Additionally, the BTGRN and BTGRP resistive bidirectional switches and the UTGRN and UTGRP resistive unidirectional switches can be assigned depths with the SERIES-DEPTH (SDEPTH) keyword-field. (The subsection Depths And Strengths in Circuit Troubleshooting describes the correspondence between series depths and drive strengths.) The series depth value may be an integer between 1 and 32,767 inclusive. If unspecified, the default series-depth is 1.

Figure 25 illustrates a sample circuit that requires proper drive strength assignments in order to model its operation. The inverter loop represents a single memory cell inside a RAM. The bit line connects to all cells associated with a particular memory bit through series transistors, only one of which is ON at any time. The write amplifier, w, drives the bit line at POWER strength. When this value propagates through the series transistor, with a series-depth of 1, its strength is reduced to DRIVING. This is strong enough to overcome the RESISTIVE strength of inverter i2, so the value of d_in is written into the memory cell.

p=w t=tpadn i=write,d_in o=bit odrive=pow
p=r t=tpend i=read,bit, o=d_out
p=x t=btgrn  i=addr  b=bit,q  sdepth=1
p=i1 t=inv i=q o=nq odrive=resistive
p=i2 t=inv i=nq o=q

Figure 25 - Memory Cell Read/Write Circuit