Simulation Options

Overview

SIMIC is a very comprehensive simulator, with many user-controlled options. This chapter explains the simulation options summarized in the options banner, which is generated at the start of PRINT or WRITE output (see Simulation Output). Where necessary, it also indicates the chapters of this Guide that contain more detailed descriptions of these options.

A typical options banner might appear as follows:

Remark= Options: (Fault Free Simulation)
Remark=	Pattern Stimuli, Near Filter, Spike Propagation
Remark=	Stable After Decay, Dynamic Delay

This banner summarizes some of the main options chosen for this simulation. In addition, it is always possible to "query" SIMIC for a more detailed report of selected global options with the ?DEFINE (?DE) command:

?DEFINE

For example:

>>: ?define
Global Definitions:
Default File Name = 'noname'
Resistive Strength to Depth value = 3
Oscillation Limit = 10
Warn Message Limit = 10
Potential detect drop limit = Infinite
Pulse window multiplier = 3
Near window multiplier = 2
X-address limit = 4
Dynamic modification of delay = Yes
Propagate Spikes = Yes
Stability = After Decays

Fault Free Simulation/Fault Simulation

Fault-free simulation does not mean that the circuit is error-free; it means that SIMIC is not performing fault simulation. Fault-free simulation, sometimes called "true-value" or "good-logic" simulation, is the simulation mode for verifying circuit timing and functionality; it is the mode that has been discussed so far in this Guide. In contrast, fault simulation introduces logic faults and grades the input stimuli's ability to detect these faults. Hence, fault simulation verifies the effectiveness of test stimuli. As long as the FAULT command options are not activated, simulation will be in fault-free mode.

Pattern Stimuli/Waveform Stimuli/Timing Generators

This options banner entry reports the applied input stimulus mode, as discussed in Input Stimuli. This choice determines the interpretation of the time and test fields in the simulation output. Again, pattern mode is the most powerful for circuit analysis and debugging, if applicable. Timing generator mode, by emulating the tester environment, is the most applicable mode for defining manufacturing test programs, and debugging tester programs.

Near Filter/Near Propagation

Near hazard analysis tests timing tolerances in the circuit, and attempts to determine whether minor variation in delays could cause a timing problem. This is essentially a "what-if" analysis that examines the effects of "close" transitions at element inputs (the definition of "closeness" is user-controllable). A description of near hazard analysis can be found in SIMIC Terminology and Definitions. This is a robustness test, which may find problems that less critical methods of logic simulation miss. In near propagation mode, an X-pulse will be generated when a near hazard occurs. In near filter mode, no X-pulse will be generated. Near hazard propagation is controlled by the NEAR (NE) keyword option of the XPROPAGATE (XP) command. It is enabled with:

XPROPAGATE NEAR:

and disabled with:

NO XPROPAGATE NEAR:

The latter is SIMIC's default; if near propagation is not requested, SIMIC operates in near filter mode.

Spike Filter/Spike Propagation

A spike hazard occurs when an element output is scheduled to change and, before that time arrives, another event at the element's inputs causes the new output value to differ from the scheduled value. (This situation is also called a "glitch".) Since output delay time is primarily associated with a node's charging time, and since the occurrence of a spike indicates that the node had insufficient time to reach the previously-scheduled value, one method of handling spikes is to ignore the transient and maintain the node at its previous value. This model, called "inertial filtering", is utilized by many logic simulators. Spike filter mode, in effect, is equivalent to inertial filtering.

However, simulation is only a model of reality, and optimistic results may be obtained unless the effects of manufacturing tolerances are somehow incorporated. Spike propagation mode attempts to account for simulation uncertainties (possible differences between simulated delays and actual delays) by producing an X-pulse whenever a spike hazard occurs.

Spike propagation can be enabled or disabled globally with the SPIKE (SP) keyword option of the XPROPAGATE (XP) command. To disable spike propagation:

NO XPROPAGATE SPIKE:

and to enable it globally:

XPROPAGATE SPIKE:

By default, SIMIC propagates spikes. SIMIC actually allows the triggering condition and size of the X-pulse to be controlled on a per-node basis (see Querying and Modifying Spike Control Parameters).

Stable After Decay/Stable Before Decay

This options banner entry reports the selected definition of stability. SIMIC performs certain operations when the simulated circuit's state becomes stable—it executes actions for which the PSTEP keyword option is active (PRINT, WRITE, and BREAK every k-th stable state) and applies the next input state for pattern mode stimuli.

By definition, the circuit state is stable when internal activity in response to the current input state has ceased. The question arises whether the long time-constants of charge decay should be included in this definition. The answer depends on the application.

Obviously, it would be impossible to simulate dynamic logic with stable-state patterns if the next pattern is applied only after all charged nodes are decayed. (However, if waveforms or timing generators are used with dynamic logic, it may be necessary to know whether a node does decay during the course of simulation.) For dynamic designs, the definition of stability should not include pending decays.

Conversely, a static design's lack of dependence on clock rate would not be fully verified unless all charge is decayed before applying the next pattern. For static designs, the definition of stability should include pending decays.

Thus, the application determines the definition of stability. The DEFINE (DE) command's STABILITY (STAB) keyword option is used for this purpose. To specify the that stability does not include pending decays, use the command:

DEFINE STABILITY=PREDECAY

To include pending decays in the definition of stability:

DEFINE STABILITY=POSTDECAY

The reserved word PREDECAY and POSTDECAY may be abbreviated to two letters.

By default, SIMIC includes pending decays in the definition of stability (POSTDECAY).

Dynamic Delays/Static Delays

Since the SIMIC ideal switch primitives (BTGN and BTGP) are resistanceless devices, nodes connected through ON ideal switches should behave as if they were physically connected. Therefore, by default, SIMIC dynamically sums the loading of nodes dynamically interconnected through ON ideal switches, and then recomputes the corresponding delays for the drivers of the tied nodes.

The DEFINE command's BTGDELAY (BTGD) keyword option controls dynamic delay computation. The following command disables dynamic delay modification:

DEFINE BTGDELAY=STATIC

To enable dynamic modification of driver delays:

DEFINE BTGDELAY=DYNAMIC

The reserved word STATIC and DYNAMIC may be abbreviated to one letter.

This option has no effect on simulation if there are no BTGN or BTGP elements or if the driver delays do not depend on loading.