Stimulus Verification With Fault Analysis

Assessing the effectiveness of test stimuli to detect manufacturing defects.

Introduction

The Basic Simulation and Circuit Modeling sections describe how SIMIC can be used to verify the functionality and timing of a design. The mode of simulation covered by those topics is called good-logic or fault-free simulation.

This page describes how SIMIC can be used to assess the effectiveness of a given stimulus set to detect manufacturing defects. Here, the test stimuli are being verified, rather than the design.

The remainder of this page introduces the SIMIC options to perform this assessment, basic concepts of SIMIC fault analysis, and the SIMIC fault naming convention.

Single-Stuck Fault Model

While the number and type of manufacturing defects is large, the literature on testing indicates that if the stimulus set can detect a high percentage of single-stuck faults at the gate-level, it can usually detect a high percentage of other types of gate-level faults as well. A single-stuck fault model is constructed by forcing a single net, or a single element pin, to be permanently stuck at a particular level, either logical 0 or logical 1, while allowing all other nets and element pins in the circuit to operate properly. For input faults, the element input pin is permanently stuck at a constant level, but the net driving the pin is free to operate properly.

The literature also indicates that for switch-level faults, single stuck-ON and stuck-OFF fault models are also necessary to grade the stimulus set. In these models, a single transistor is permanently stuck ON or OFF, while all other elements operate properly. (Stuck-ON and stuck-OFF faults are equivalent to the corresponding stuck-at faults on the gate inputs of the switches.)

Fault Sensitization Analysis

Fault Sensitization Analysis is used to determine how well the stimulus set "exercises" each fault by examining whether the fault has been locally sensitized:

  1. If the fault is at an element output, then it is locally sensitized whenever the correct output value is the complement of the stuck-at value; for example, a stuck-at-0 fault is locally sensitized whenever the correct output value is logical 1. (The "toggle test" is a well-known variant of output fault sensitization analysis; it checks whether the stimulus set drives each element output to both logical 0 and logical 1.)
  2. If the fault is at an element input, then it is locally sensitized if any element output would be different, depending on whether the fault were present or absent.

Fault Sensitization Analysis is fast, since it is performed during ordinary (good-logic) simulation. Since a fault must be sensitized in order to be detected, this analysis can be used to determine which faults cannot be detected by the stimulus set, and to provide an upper bound on the number of faults that can be detected by the stimulus set (assuming the effects of all sensitized faults are detected at the device outputs).

Fault Sensitization Analysis is invoked with the SENSITIZE (SEN) command. Sensitization Analysis describes the options supported for sensitization analysis.

Fault Simulation

Fault Simulation is used to determine whether the stimulus set causes the effects of user-specified faults to be detected at the device outputs. It simulates the fault-free circuit and many faulty circuits concurrently, and compares the response of each faulty circuit to the response of the fault-free circuit. A fault is:

  1. detected if at least one output of the faulty circuit differs in a known manner from the corresponding output of the fault-free circuit, when the device outputs are strobed or examined. That is, the good output is logical 0 (logical 1) while the faulty output is logical 1 (logical 0), or, for tristatable outputs, the good output is undriven while the faulty output is driven.
  2. potentially detected if the only difference between the good and faulty outputs is that at least one faulty output is unknown (X), and the corresponding good output value is known, when the device outputs are strobed or examined.

The SIMIC fault simulation engine is invoked with the FAULT (FA) command. Fault Simulation describes the options supported for fault simulation.

Complete And Collapsed Fault Sets

Some faults can produce exactly the same simulation results, as observed from the primary (device) outputs. For example, consider a stuck-at-0 fault at the output of an internal AND gate, and the stuck-at-0 faults at each of the AND gate's inputs. All these faults produce the same effect, namely, the faulty AND gate output will always be logical 0, and all primary outputs in the AND gate's fanout cone will respond to the input stimuli in the identical manner, regardless of which fault is actually present.

Faults that produce exactly the same faulty circuit response, regardless of the test vectors, are indistinguishable, and are called equivalent. Stuck-at-1 faults at the output and inputs of an OR gate are another example of equivalent faults. A third example of equivalent faults are the stuck-at-1 (stuck-at-0) fault at an internal signal that drives a single load pin, and the stuck-at-1 (stuck-at-0) fault at the load's input pin.

SIMIC divides all faults into equivalence groups, where all faults in each group are equivalent. Any set of faults obtained by selecting exactly one fault from each equivalence group is called a collapsed fault set.

Inherently Undetectable Faults

SIMIC automatically removes from consideration two categories of faults that can never be detected.

The first excluded category are faults at elements that have no topological path to any primary output (e.g., unused gates within standard cells). SIMIC designates these faults as invisible faults, since they can never affect any circuit output.

The second excluded category are faults that are either (a) equivalent to ONE-stuck-at-1 or ZERO-stuck-at-0, or (b) masked by connections to ONE or ZERO. An example of the first situation would be the stuck-at-1 fault at a flip-flop NS (active-low set) or NR (active-low reset) input that is connected to ONE to disable that pin. An example of the second situation would be faults at the first input of an AND gate whose second input is tied to ZERO.

SIMIC Fault Naming Conventions

SIMIC fault designations contain either signal names or primitive part and pin names, and stuck-at values:

Signal Names for Output Faults

Signal names are used to specify output faults:

Part and Pin Names for Input or Output Faults

Part and pin names of primitives can be used to specify either input or output faults. The primitive element can either be built-in or user-defined (see Appendix A for the pin names of SIMIC built-in primitives):

Fault Naming Shortcuts

SIMIC will always report faults using the above formats. However, for specifying faults to SIMIC, you can additionally use the following notations for brevity:

Fault Naming Rules

Fault names must conform to the following rules in order to be valid:

Mutual Exclusivity Of FAULT And SENSITIZE Run Commands

The SENSITIZE command invokes fault sensitization analysis within the good-logic simulator, while the FAULT command invokes fault simulation. Thus, these commands are mutually exclusive. If you happen to specify both commands in the same session, SIMIC performs the last issued command.