RAM Primitives
Random Access Memory elements for modeling storage in digital circuits.
Overview
Simic provides three RAM primitive types, each optimized for different memory architectures and control schemes. All RAM primitives support dynamic data initialization and X-handling for robust simulation.
RAM Variants
RAMA - Single Port RAM
Standard single-port RAM with clocked write operation. Write occurs on the rising edge of the clock signal when both Chip Select (CS) and Write Enable (WE) are asserted.
Key Features:
- Single address port for both read and write operations
- Clock-synchronized writes
- Combinational reads (when RE is high)
- Tri-state outputs controlled by CS and RE
Type=RAMA i=CS,RE,WE,C,ADDR[m:0],DATAIN[n:0] o=DATA[n:0]RAMB - Dual Port RAM
Dual-port RAM with independent read and write address buses. Allows simultaneous read and write operations to different memory locations.
Key Features:
- Separate read address (RADDR) and write address (WADDR) buses
- Independent read and write control
- Supports concurrent access to different locations
- Ideal for FIFO and dual-access buffer implementations
Type=RAMB i=CS,RE,WE,RADDR[m:0],WADDR[m:0],DATAIN[n:0] o=DATA[n:0]RAMC - RAM with Address Enable
RAM variant with an additional Address Enable (AE) control signal. The address is latched when AE is asserted, allowing for address setup/hold timing control.
Key Features:
- Address Enable (AE) pin for explicit address latching
- Address is sampled and held when AE transitions
- Provides finer control over address timing
- Useful for modeling address multiplexing schemes
Type=RAMC i=CS,RE,WE,AE,ADDR[m:0],DATAIN[n:0] o=DATA[n:0]Common Features
Memory Initialization
All RAM types support initialization through the DATA keyword in the PART statement or dynamically using the CLAMP command:
# Static initialization in netlist
PART=U1 TYPE=RAMA DATA=X0, 00, 01, 02, 03
# Dynamic population in run script
CLAMP PART=U1 DATA=X1FC AA BB CCX-Handling
All RAM primitives implement consistent X-handling behavior:
- Read Operations: If CS or RE is X, outputs are X. If any address bit is X, all matching locations are read; differing values result in X.
- Write Operations: X-transitions on control signals or X-bits in addresses during valid writes cause affected memory locations to be set to X.
- MAXX Parameter: If X-bits in the address exceed the
MAXXthreshold, the entire memory or output is forced to X.
Tri-State Outputs
All RAM variants drive their DATA output to high-impedance (Z) when either:
- Chip Select (CS) is low
- Read Enable (RE) is low
Memory Size
Address and data widths are specified via bus notation in the type instantiation:
- Address Width:
ADDR[m:0]supports 2m+1 memory locations - Data Width:
DATA[n:0]andDATAIN[n:0]specify n+1 bit words
Choosing the Right RAM Type
| Use Case | Recommended Type |
|---|---|
| Simple single-port memory (processor data memory, register files) | RAMA |
| FIFO buffers, dual-access buffers, video frame buffers | RAMB |
| Multiplexed address buses, DRAM-like timing control | RAMC |