Electrical Attributes

Understanding basic timing, loading, and drive strength parameters.

Introduction

SIMIC provides comprehensive support for modeling electrical characteristics of circuits. Delays can be specified either locally (in PART/TYPE statements) or globally (in delay tables), and can depend on signal loading. The compiler automatically totals pin loading on each net and computes resultant delays based on driver characteristics.

Delays can also be changed at runtime using the SET command, allowing exploration of timing variations without recompiling the circuit.

Electrical Attribute Keywords

The following table summarizes all electrical attribute keywords available in PART and TYPE statements. See the SNL Keywords Reference for complete details on abbreviation rules.

Keyword Alias Description Default
Delay Specification (Global)
OUTPUT-DELAY ODEL Output delay (references global DELAY statement) 0
BUS-DELAY BDEL Bus delay (references global DELAY statement) 0
Delay Specification (Local)
OUTPUT-RISE ORISE Output rise delay (local specification) 0
OUTPUT-FALL OFALL Output fall delay (local specification) 0
OUTPUT-CHANGE OCHANGE Output rise/fall delay (when equal) 0
BUS-RISE BRISE Bus rise delay (local specification) 0
BUS-FALL BFALL Bus fall delay (local specification) 0
BUS-CHANGE BCHANGE Bus rise/fall delay (when equal) 0
Loading
INPUT-LOADS ILOD Input pin loading (capacitance) 0
OUTPUT-LOADS OLOD Output pin loading (driver's own capacitance) 0
BUS-LOADS BLOD Bus pin loading (capacitance) 0
Drive Strength (see Signal Behavior)
OUTPUT-DRIVE ODRIVE Output drive strength (high and low) 5 (medium)
BUS-DRIVE BDRIVE Bus drive strength (high and low) 5 (medium)
OUTPUT-HDRIVE OHDRIVE Output high drive strength 5
OUTPUT-LDRIVE OLDRIVE Output low drive strength 5
Signal Decay (see Signal Behavior)
OUTPUT-DECAY ODECAY, ODEC Output decay time to hi-Z 0 (instant)
BUS-DECAY BDECAY, BDEC Bus decay time to hi-Z 0 (instant)
Wire-Tie Resolution (see Signal Behavior)
OUTPUT-DOMINANCE ODOM Output dominance (0=wired-AND, 1=wired-OR, X=conflict) X
BUS-DOMINANCE BDOM Bus dominance (0=wired-AND, 1=wired-OR, X=conflict) X
Spike Filtering (see Signal Behavior)
OUTPUT-FILTER OFILTER Output spike filter (% of delay or absolute) 0
BUS-FILTER BFILTER Bus spike filter (% of delay or absolute) 0
OUTPUT-LIBERAL OLIBERAL Output liberal parameter (delays X propagation) 0
BUS-LIBERAL BLIBERAL Bus liberal parameter (delays X propagation) 0
Keyword Naming: Full keywords use hyphens (e.g., OUTPUT-DELAY). Aliases omit hyphens (e.g., ODEL). Keywords beginning with OUTPUT- apply to outputs, BUS- to buses, and INPUT- to inputs.

SIMIC Time-Units

A time-unit is the smallest quantum of time that can be processed. All delays are expressed in time-units, which are normalized measurements that can represent any real-time value (picoseconds, nanoseconds, etc.).

Selecting Time Scale

Care must be taken when selecting the scale factor. If technology has gate delays in the nanosecond range and you scale 1 time-unit = 1 picosecond, each delay will be thousands of time-units. Since SIMIC maintains elapsed time as a 32-bit integer, maximum simulation time is 2,147,483,647 time-units.

Specifying Time-Units

!DELAY time-units=1e-9

This specifies that one time-unit corresponds to one nanosecond. SIMIC reports this correspondence at runtime.

Best Practice: Choose time-units so that typical gate delays are in the range of 5-50 time-units. This balances precision with maximum simulation time.

Delay Specification Formats

Delays are specified using fixed-point or floating-point numbers with up to six significant digits.

Number Formats

The plus sign for positive exponents is optional. The number 72 can be represented as 72, 72., 7200e-2, .0072e4, etc.

Linear Delay Curves

For technologies where propagation delays depend linearly on capacitive loading, SIMIC provides two equivalent forms:

Two-Point Form

Defines a line passing through two coordinates:

(load1,delay1)(load2,delay2)

Example: (2,4)(6,8) defines a delay of 4 at loading 2, and 8 at loading 6.

Intercept-Slope Form

Defines a line by its y-intercept and slope:

[intercept,slope]

Example: [2,1] is equivalent to (2,4)(6,8).

Constant Delays

Constant delays (zero slope) can be specified as:

Note: If delays depend on input slew-rate or vary non-linearly with loading, use the advanced Ctable (piecewise linear loading curves) or Rtable (segmented slew-rate tables) formats described in Advanced Delay Modeling.

Global Delays

Global delays are specified in the !DELAY section and assigned unique names that are referenced by PART and TYPE statements in the !LOGICAL section.

Basic Syntax

For different rise and fall delays:

DELAY=<name> RISE=<delay> FALL=<delay>

For identical rise and fall delays:

DELAY=<name> CHANGE=<delay>

Example: Defining Global Delays

!DELAY time-units=1e-9

DELAY=del5 RISE=[2,1] FALL=7
DELAY=fast_inv CHANGE=[1,0.5]

Min/Typ/Max Delays

Delays can include minimum, typical, and maximum values:

DELAY=del12_8_15 CHANGE=[12,1];8;(0,15)(2,19)

Format: typical;minimum;maximum. If min or max is omitted, it defaults to the typical value.

Assigning Global Delays

Reference global delays using ODEL (outputs) or BDEL (busses):

!LOGICAL

p=a2 t=full-adder i=a[2],b[2],c[1] o=s[2],c[2] odel=del5,del12_8_15

This assigns del5 to output s[2] and del12_8_15 to c[2].

Placeholder Commas: To skip delays, use a comma: odel=,del12_8_15 assigns zero delay to the first output and del12_8_15 to the second.

Local Delays

Delays can be assigned locally within PART or TYPE statements without referencing global delays. This is useful for automated netlisters.

Keywords

Example: Local Delay Assignment

t=my_type i=a,b,c b=d,e o=f,g bchange=3,4 $
    orise=(5,3)(20,4) ofall=[3,1] ochange=,2

This assigns:

Pin Loading

Pin loading represents input capacitance. SIMIC totals all pin loading on each net (including wiring capacitance) to compute resultant driver delays.

Loading Keywords

Example: Specifying Loading

t=my_type i=a,b,c b=d,e o=f,g $
    ilod=1,,3 blod=5;4;6,7.89 olod=10,11

This assigns:

Adding Net Loading with LOAD Primitive

Assign loading to nets (representing wiring capacitance) using the built-in LOAD element:

* Explicit output name:
p=load_elem t=load o=signal_name olod=3

* Part name is net name:
p=signal_name t=load olod=3

* With min/typ/max:
p=a.b.c t=load olod=3;2;5

Resultant Delays

When load-dependent driver delay is specified, SIMIC totals all loading on the driven net to compute the resultant delay. Calculations are performed in floating point and rounded to the nearest integer.

Example: Delay Calculation

p=driver t=and i=a,b o=signal orise=[5,2] ofall=[3,1] olod=1.1
p=load1 t=inv i=signal ilod=2.6
p=load2 t=inv i=signal ilod=2.5
p=signal t=load olod=3.4

Total loading on signal = 1.1 + 2.6 + 2.5 + 3.4 = 9.6

Note: If the computed delay is negative after interpolation, SIMIC sets it to 0.

Practical Tips

Global vs. Local Delays

Use Global When... Use Local When...
Building technology libraries Using automated netlisters
Supporting multiple process variants Unique per-instance timing
Reusing delay definitions across files Quick prototyping

Runtime Delay Modification

Use the SET command to explore timing variations:

>>: set rise=10 fall=15 list=signal_a,signal_b
>>: set change=5 list:
>>: simulate
Important: Use RISE, FALL, or CHANGE keywords with LIST to modify delays. The CHANGE keyword cannot be combined with RISE or FALL. Use LIST: for all signals or LIST=name1,name2 for specific signals.