Case Study: Divide-by-7 Counter
Debugging spike hazards and X-pulse propagation in a counter circuit.
Overview
The Divide-by-7 counter shown in Figure 9 has a potential timing hazard that only becomes apparent when spikes are allowed to propagate. This indicates a timing problem that may manifest itself in non-functioning devices, or in reduced yields. This example demonstrates the necessity of a robust spike propagation algorithm. In addition, it demonstrates some of SIMIC's interactive debugging capabilities, and provides a brief description of these capabilities.
In this circuit, three negative edge T flip-flops (built-in primitive TCF) are initially reset to a count of 000 (q4, q2, q1). When the counter reaches state 110 on the sixth negative-going clock edge, signal set goes low, forcing a counter state of 111, which makes signal set go high again. The next CLOCK pulse causes the counter state to return to 000. (Note: the OCHANGE, or OUTPUT-CHANGE SNL keyword assigns identical rise and fall delays to an output; thus, signal nreset has a delay of 1, signal q1 has a delay of 2, etc.)
Circuit Description
Figure 9 - Divide-by-7 Counter
SNL Network Definition
The circuit is defined in div.net:
C= SNL Description of divide by 7 circuit
!f p= t= i= o= ochange=
type=divide_by_7 i=reset,clock o=q1,q2,q4
nreset inv reset - 1
q1 tcf nreset,set,clock q1 2
q2 tcf nreset,one,q1 q2 2
q4 tcf nreset,one,q2 q4 2
nq1 inv q1 - 1
Set nand nq1,q2,q4 - 1Run 1: Spike Filtering Enabled
By default, SIMIC propagates an X-pulse whenever a spike hazard occurs. To demonstrate the importance of X-pulse propagation, the first simulation of the Divide-by-7 circuit is performed without it. This is accomplished by issuing the NO XPROPAGATE SPIKE: run command (spike filter mode).
Simulation Output
The SIMIC Logic simulator... Version 1.09.01
>>: define fi=div
>>: get type=divide_by_7
Main Get Network : DIVIDE_BY_7
Using file: "div.net"
GET completed, Circuit totals: Parts = 6; Signals = 10
Inputs = 2; Busses = 0; Outputs = 3
>>: define pr.1 = 1 0
>>: define pc.1 = 0 0 do 8 (1 0)
>>: apply patterns=pc list=clock
>>: apply patterns=pr list=reset
>>: print li=reset*clock**q1,q2,q4*set
>>: no xpropagate spike:
>>: simulate
Main Get Timing : TYPICAL Circuit Delays
Remark= Options: (Fault-Free Simulation)
Remark= Pattern Stimuli, Near Filter, Spike Filter
Remark= Stable After Decay, Dynamic Delay, No Charge Sharing
C= R C QQQ S
C= E L 124 E
C= S O T
C= E C
C= T K
7 T 1: 1 0 000 1
1 T 2: 0 0 000 1
2 T 3: 0 1 000 1
4 T 4: 0 0 100 1
2 T 5: 0 1 100 1
6 T 6: 0 0 010 1
2 T 7: 0 1 010 1
4 T 8: 0 0 110 1
2 T 9: 0 1 110 1
6 T 10: 0 0 001 1
2 T 11: 0 1 001 1
4 T 12: 0 0 101 1
2 T 13: 0 1 101 1
9 T 14: 0 0 111 1
2 T 15: 0 1 111 1
6 T 16: 0 0 000 1
2 T 17: 0 1 000 1
4 T 18: 0 0 100 1
2 Spike messages suppressed.Analysis
This simulation, called Run 1, is shown in Figure 10. Based on these results, which would be obtained from simulators that do not support spike propagation, the counter appears to behave as predicted, and therefore the design might be assumed to be correct and problem-free.
Although spike propagation was inhibited, SIMIC still issued a warning that two unreported spikes occurred during simulation. In general, SIMIC will count the number of unreported spikes that occur during simulation (even if spike warning messages have been suppressed or have not been requested) and will report this number at the end of each simulation run.
Because of the post-simulation warning that unreported spikes occurred, the simulation is repeated, this time allowing spikes to propagate. This is accomplished simply by eliminating the NO XPROPAGATE SPIKE: command, since spike propagation is SIMIC's default.
Run 2: Spike Propagation Enabled (Default)
Simulation Output
>>: define file=div
>>: get type=divide_by_7
Main Get Network : DIVIDE_BY_7
Using file: "div.net"
GET completed, Circuit totals: Parts = 6; Signals = 10
Inputs = 2; Busses = 0; Outputs = 3
>>: define pr.1 = 1 0
>>: define pc.1 = 0 0 do 8 (1 0)
>>: apply patterns=pc list=clock
>>: apply patterns=pr list=reset
>>: print li=reset*clock**q1,q2,q4*set
>>: simulate
Main Get Timing : TYPICAL Circuit Delays
Remark= Options: (Fault-Free Simulation)
Remark= Pattern Stimuli, Near Filter, Spike Propagation
Remark= Stable After Decay, Dynamic Delay, No Charge Sharing
C= R C QQQ S
C= E L 124 E
C= S O T
C= E C
C= T K
7 T 1: 1 0 000 1
1 T 2: 0 0 000 1
2 T 3: 0 1 000 1
4 T 4: 0 0 100 1
2 T 5: 0 1 100 1
6 T 6: 0 0 010 1
2 T 7: 0 1 010 1
4 T 8: 0 0 110 1
2 T 9: 0 1 110 1
6 T 10: 0 0 001 1
2 T 11: 0 1 001 1
4 T 12: 0 0 101 1
2 T 13: 0 1 101 1
9 T 14: 0 0 111 1
2 T 15: 0 1 111 1
10 T 16: 0 0 XXX X
0 T 17: 0 1 XXX X
0 T 18: 0 0 XXX X
2 Spike messages suppressed.Analysis
This simulation session, called Run 2, is shown in Figure 11. As a result of spike propagation, q1, q2, and q4 went unknown (X) at test 16. This is an indication that the spikes do indeed introduce a critical timing problem.
Having determined that a problem exists, the next step is to perform interactive debugging to determine its cause. The simulation will be run again, and a breakpoint will be set to "freeze" the simulation when a spike occurs. This is accomplished with the
BREAK SPIKE: MEMSPIKE:
run command. SIMIC can distinguish spikes in memory elements (MEMSPIKE) from other spikes (SPIKE). The SPIKE: option in the BREAK command requests a break from simulation if any spike (including spikes in memory elements) is occurs. Although this would have been sufficient for this example, the MEMSPIKE: option is used to request a break if a spike occurs in a flip-flop primitive (a subset of the SPIKE: option). As a result, a spike at a memory element will be reported as a MEMSPIKE, rather than as a SPIKE.
Run 3: Debugging the Hazard
Part 1: Setting Breakpoint on Spike
>>: define file=div
>>: get type=divide_by_7
Main Get Network : DIVIDE_BY_7
Using file: "div.net"
GET completed, Circuit totals: Parts = 6; Signals = 10
Inputs = 2; Busses = 0; Outputs = 3
>>: define pr.1 = 1 0
>>: define pc.1 = 0 0 do 8 (1 0)
>>: apply patterns=pc list=clock
>>: apply patterns=pr list=reset
>>: print li=reset*clock**q1,q2,q4*set
>>: break spike: memspike:
>>: simulate
Main Get Timing : TYPICAL Circuit Delays
Remark= Options: (Fault-Free Simulation)
Remark= Pattern Stimuli, Near Filter, Spike Propagation
Remark= Stable After Decay, Dynamic Delay, No Charge Sharing
C= R C QQQ S
C= E L 124 E
C= S O T
C= E C
C= T K
7 T 1: 1 0 000 1
1 T 2: 0 0 000 1
2 T 3: 0 1 000 1
4 T 4: 0 0 100 1
2 T 5: 0 1 100 1
6 T 6: 0 0 010 1
2 T 7: 0 1 010 1
4 T 8: 0 0 110 1
2 T 9: 0 1 110 1
6 T 10: 0 0 001 1
2 T 11: 0 1 001 1
4 T 12: 0 0 101 1
2 T 13: 0 1 101 1
9 T 14: 0 0 111 1
2 T 15: 0 1 111 1
5 B 16> MEMSPIKE(0->1->0) Q1.1
5 B 16> MEMSPIKE(0->1->0) Q1
Figure 12 illustrates the results of this simulation, called Run 3. SIMIC stops the simulation at test 16, issues two MEMSPIKE BREAK messages, and reports that spikes originate at both the master, q1.1, and slave, q1, of flip-flop q1.
At this point, the simulation is frozen at time 5 of test 16, and SIMIC has issued its prompt requesting a command. In order to obtain more information about the cause of the spike, the circuit's response to test 16 will be resimulated. This time, however, all activity will be traced to determine the sequence of events that lead to the spike. As before, SIMIC will break from simulation when the spike occurs, since the BREAK command is still active (the BREAK can only be removed with a NO BREAK command).
Part 2: Using TRACE to Analyze Causality
The command:
restore tnum=*
rolls time back to the beginning of the current test (the last stable state), so when the SIMULATE command is issued, test 16 will be resimulated.
The command:
trace list: expand:
causes the activity at every signal to be traced. Additionally, use of the EXPAND option causes the trace output to be augmented with causality information.
>>: restore tnum=*
>>: trace list: expand:
>>: simulate
Remark= Options: (Fault-Free Simulation)
Remark= Pattern Stimuli, Near Filter, Spike Propagation
Remark= Stable After Decay, Dynamic Delay, No Charge Sharing
C= R C QQQ S
C= E L 124 E
C= S O T
C= E C
C= T K
0 E 16> TRACE(1->0) CLOCK
2 E 16> TRACE(1->0) Q1
C > (1->0) CLOCK
3 E 16> TRACE(0->1) NQ1
C > (1->0) Q1
4 E 16> TRACE(1->0) Q2
C > (1->0) Q1
4 E 16> TRACE(1->0) SET
C > (0->1) NQ1
C > (1->0) Q2
5 E 16> TRACE(0->1) SET
C > (1->0) Q2
5 B 16> MEMSPIKE(0->1->0) Q1.1
5 B 16> MEMSPIKE(0->1->0) Q1
5 E 16> TRACE(0->X) Q1.1
C > (0->1) SET
5 E 16> TRACE(0->X) Q1
C > (0->1) SETAnalysis of TRACE Output
The results of resimulating test 16 with activity trace are shown in Figure 13. (Note that this is still the same session, Run 3.) SIMIC breaks from simulation at time 5 of test 16, as before. Even a cursory examination of the TRACE output indicates that a unit-width pulse occurs on signal set; it executes a 1→0 transition at time 4 and a 0→1 transition at time 5. This pulse is not wide enough to actually set flip-flop q1, whose rise delay is 2 time-units.
Causality information, in turn, indicates that the pulse (which shouldn't exist at all) is due to a race condition between nq1 and q2. Therefore, it should be possible to eliminate the spike by increasing the delay of nq1 to make its 0→1 transition occur after the transition at q2. The required delay modification would be from its current value of 1 to any value greater than 2 (say, 3).
Part 3: Fixing the Hazard
At any point when the circuit is in a "frozen" state (simulation is stopped by a break), commands can be entered to modify parameters and/or signal values as well as to request information about the circuit's state, topology and electrical characteristics.
Figure 14 shows the simulation results when this fix is made interactively. As before, the command:
restore tnum=*
rolls time back to the beginning of the current test, so when the SIMULATE command is issued, test 16 will be re-simulated. The propagation delay of NQ1 is modified with the command:
set change=3 list=nq1
The activity trace, no longer necessary, is removed with the command:
no trace list:
Resimulation shows that, indeed, no spike occurs with this modification:
>>: restore tnum=*
>>: set change=3 list=nq1
>>: notrace list:
>>: simulate
Remark= Options: (Fault-Free Simulation)
Remark= Pattern Stimuli, Near Filter, Spike Propagation
Remark= Stable After Decay, Dynamic Delay, No Charge Sharing
C= R C QQQ S
C= E L 124 E
C= S O T
C= E C
C= T K
6 T 16: 0 0 000 1
2 T 17: 0 1 000 1
5 T 18: 0 0 100 1At this point, it is suggested that the simulation be repeated for the full stimulus sequence, to make sure that no new problems have been introduced at other points in the test sequence.